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Hardware Support for Relaxed Concurrency Control in Transactional Memory
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/11864219_20openalex-snapshot
A Lazy Snapshot Algorithm with Eager Validation
inferredcites →https://doi.org/10.1109/2.982916openalex-snapshot
Simics: A full system simulation platform
inferredcites →https://doi.org/10.1109/hpca.2007.346204openalex-snapshot
LogTM-SE: Decoupling Hardware Transactional Memory from Caches
inferredcites →https://doi.org/10.1109/iiswc.2008.4636089openalex-snapshot
STAMP: Stanford Transactional Applications for Multi-Processing
inferredcites →https://doi.org/10.1109/isca.1993.698569openalex-snapshot
Transactional Memory: Architectural Support For Lock-free Data Structures
inferredcites →https://doi.org/10.1109/isca.2004.1310767openalex-snapshot
Transactional memory coherence and consistency
inferredcites →https://doi.org/10.1109/isca.2006.13openalex-snapshot
Bulk Disambiguation of Speculative Threads in Multiprocessors
inferredcites →https://doi.org/10.1109/isca.2008.17openalex-snapshot
Flexible Decoupled Transactional Memory Support
inferredcites →https://doi.org/10.1109/micro.2008.4771795openalex-snapshot
Dependence-aware transactional memory for increased concurrency
inferredcites →https://doi.org/10.1145/1105734.1105747openalex-snapshot
Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset
inferredcites →https://doi.org/10.1145/1150019.1136506openalex-snapshot
Bulk Disambiguation of Speculative Threads in Multiprocessors
inferredcites →https://doi.org/10.1145/1229428.1229441openalex-snapshot
Transactional collection classes
inferredcites →https://doi.org/10.1145/1250662.1250674openalex-snapshot
Performance pathologies in hardware transactional memory
inferredcites →https://doi.org/10.1145/1273440.1250674openalex-snapshot
Performance pathologies in hardware transactional memory
inferredcites →https://doi.org/10.1145/1394608.1382134openalex-snapshot
Flexible Decoupled Transactional Memory Support
inferredcites →https://doi.org/10.1145/1504176.1504201openalex-snapshot
Committing conflicting transactions in an STM
inferredcites →https://doi.org/10.1145/339647.339650openalex-snapshot
A scalable approach to thread-level speculation
inferredcites →https://doi.org/10.1145/342001.339650openalex-snapshot
A scalable approach to thread-level speculation
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-3-642-38027-3_35openalex-snapshot
DDASTM: Ensuring Conflict Serializability Efficiently in Distributed STM
inferred← citeshttps://doi.org/10.1109/cluster.2016.79openalex-snapshot
Conflict Prediction-Based Transaction Execution for Transactional Memory in Multi-core In-memory Databases
inferred← citeshttps://doi.org/10.1109/hpca.2012.6168952openalex-snapshot
BulkSMT: Designing SMT processors for atomic-block execution
inferred← citeshttps://doi.org/10.1109/icacci.2016.7732076openalex-snapshot
Checkpoint based multi-version concurrency control mechanism for remote healthcare system
inferred← citeshttps://doi.org/10.1109/ipdps57955.2024.00081openalex-snapshot
LockillerTM: Enhancing Performance Lower Bounds in Best-Effort Hardware Transactional Memory
inferred← citeshttps://doi.org/10.1109/ipdpsw.2012.320openalex-snapshot
On the Correctness of Mixing Lazy and Eager Version Management in Transactions
inferred← citeshttps://doi.org/10.1109/isca.2014.6853223openalex-snapshot
OmniOrder: Directory-based conflict serialization of transactions
inferred← citeshttps://doi.org/10.1109/micro.2016.7783737openalex-snapshot
Exploiting semantic commutativity in hardware speculation
inferred← citeshttps://doi.org/10.1109/micro.2018.00026openalex-snapshot
Harmonizing Speculative and Non-Speculative Execution in Architectures for Ordered Parallelism
inferred← citeshttps://doi.org/10.1109/micro50266.2020.00051openalex-snapshot
Unbounded Hardware Transactional Memory for a Hybrid DRAM/NVM Memory System
inferred← citeshttps://doi.org/10.1109/micro61859.2024.00067openalex-snapshot
Chaining Transactions for Effective Concurrency Management in Hardware Transactional Memory
inferred← citeshttps://doi.org/10.1109/pact.2017.37openalex-snapshot
SAM: Optimizing Multithreaded Cores for Speculative Parallelism
inferred← citeshttps://doi.org/10.1109/pact.2019.00038openalex-snapshot
Multiversioned Page Overlays: Enabling Faster Serializable Hardware Transactional Memory
inferred← citeshttps://doi.org/10.1145/2400682.2400701openalex-snapshot
An integrated pseudo-associativity and relaxed-order approach to hardware transactional memory
inferred← citeshttps://doi.org/10.1145/2633048openalex-snapshot
Effective Transactional Memory Execution Management for Improved Concurrency
inferred← citeshttps://doi.org/10.1145/2693260openalex-snapshot
Efficient Correction of Anomalies in Snapshot Isolation Transactions
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