On the public citation graph
ScalableBulk: Scalable Cache Coherence for Atomic Blocks in a Lazy Environment
0 signed · 41 inferred · view as graph
Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.
Is this your work? Sign in with ORCID and put your name on the
claims that are yours.
Reference health. See whether every reference in this work resolves to a
known work and none has been retracted — and get a dated CiteStamped
badge you can embed.
What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1109/hpca.2007.346189openalex-snapshot
A Scalable, Non-blocking Approach to Transactional Memory
inferredcites →https://doi.org/10.1109/hpca.2007.346204openalex-snapshot
LogTM-SE: Decoupling Hardware Transactional Memory from Caches
inferredcites →https://doi.org/10.1109/hpca.2009.4798252openalex-snapshot
Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs
inferredcites →https://doi.org/10.1109/isca.2004.1310767openalex-snapshot
Transactional memory coherence and consistency
inferredcites →https://doi.org/10.1109/isca.2006.13openalex-snapshot
Bulk Disambiguation of Speculative Threads in Multiprocessors
inferredcites →https://doi.org/10.1109/isca.2008.36openalex-snapshot
DeLorean: Recording and Deterministically Replaying Shared-Memory Multiprocessor Execution Ef?ciently
inferredcites →https://doi.org/10.1109/isca.2008.4openalex-snapshot
Atom-Aid: Detecting and Surviving Atomicity Violations
inferredcites →https://doi.org/10.1109/perser.2005.1506430openalex-snapshot
Implementing kilo-instruction multiprocessors
inferredcites →https://doi.org/10.1109/tpds.2002.1011412openalex-snapshot
Specifying and verifying a broadcast and a multicast snooping cache coherence protocol
inferredcites →https://doi.org/10.1145/1028176.1006711openalex-snapshot
Transactional Memory Coherence and Consistency
inferredcites →https://doi.org/10.1145/1150019.1136506openalex-snapshot
Bulk Disambiguation of Speculative Threads in Multiprocessors
inferredcites →https://doi.org/10.1145/1250662.1250673openalex-snapshot
An effective hybrid transactional memory system with strong isolation guarantees
inferredcites →https://doi.org/10.1145/1250662.1250674openalex-snapshot
Performance pathologies in hardware transactional memory
inferredcites →https://doi.org/10.1145/1250662.1250684openalex-snapshot
Hardware atomicity for reliable software speculation
inferredcites →https://doi.org/10.1145/1250662.1250696openalex-snapshot
Mechanisms for store-wait-free multiprocessors
inferredcites →https://doi.org/10.1145/1454115.1454137openalex-snapshot
Scalable and reliable communication for hardware transactional memory
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1109/hpca.2012.6168951openalex-snapshot
π-TM: Pessimistic invalidation for scalable lazy hardware transactional memory
inferred← citeshttps://doi.org/10.1109/hpca.2012.6168952openalex-snapshot
BulkSMT: Designing SMT processors for atomic-block execution
inferred← citeshttps://doi.org/10.1109/hpca.2012.6169040openalex-snapshot
BulkCompactor: Optimized deterministic execution via Conflict-Aware commit of atomic blocks
inferred← citeshttps://doi.org/10.1109/ipdps47924.2020.00027openalex-snapshot
Transaction-Based Core Reliability
inferred← citeshttps://doi.org/10.1109/lca.2018.2791433openalex-snapshot
Core Reliability: Leveraging Hardware Transactional Memory
inferred← citeshttps://doi.org/10.1109/micro.2016.7783708openalex-snapshot
Data-centric execution of speculative parallel programs
inferred← citeshttps://doi.org/10.1109/micro.2016.7783737openalex-snapshot
Exploiting semantic commutativity in hardware speculation
inferred← citeshttps://doi.org/10.1109/pact.2011.41openalex-snapshot
Pi-TM: Pessimistic Invalidation for Scalable Lazy Hardware Transactional Memory
inferred← citeshttps://doi.org/10.1109/pact.2019.00023openalex-snapshot
Forgive-TM: Supporting Lazy Conflict Detection In Eager Hardware Transactional Memory
inferred← citeshttps://doi.org/10.1145/2875425openalex-snapshot
Power Efficient Hardware Transactional Memory
inferred← citeshttps://doi.org/10.1145/3352460.3358321openalex-snapshot
Distributed Logless Atomic Durability with Persistent Memory
inferred← citeshttps://doi.org/10.5821/dissertation-2117-94562openalex-snapshot
Architectural support for high-performing hardware transactional memory systems
inferred← citeshttps://doi.org/10.5821/dissertation-2117-95386openalex-snapshot
Techniques to improve concurrency in hardware transactional memory
Editorial review for independent work. ICSAC — the Institute for Complexity
Science and Advanced Computing — runs a structured editorial panel for researchers
publishing outside journals, and publishes on CiteStamp rails. Submission is free
and goes through ORCID: icsacinstitute.org/submit.