On the public citation graph

ASF: AMD64 Extension for Lock-Free Data Structures and Transactional Memory

https://doi.org/10.1109/micro.2010.40
0 signed · 82 inferred · view as graph

Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.

Is this your work? Sign in with ORCID and put your name on the claims that are yours.
Claim with ORCID
Reference health. See whether every reference in this work resolves to a known work and none has been retracted — and get a dated CiteStamped badge you can embed.
See reference health

What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/978-3-540-30186-8_9openalex-snapshot
An Optimistic Approach to Lock-Free FIFO Queues
inferredcites →https://doi.org/10.1007/s00446-007-0050-0openalex-snapshot
An optimistic approach to lock-free FIFO queues
inferredcites →https://doi.org/10.1023/a:1007699313329openalex-snapshot
inferredcites →https://doi.org/10.1109/hpca.2006.1598134openalex-snapshot
LogTM: Log-based Transactional Memory
inferredcites →https://doi.org/10.1109/hpca.2006.1598135openalex-snapshot
The Common Case Transactional Behavior of Multithreaded Programs
inferredcites →https://doi.org/10.1109/hpca.2007.346204openalex-snapshot
LogTM-SE: Decoupling Hardware Transactional Memory from Caches
inferredcites →https://doi.org/10.1109/iiswc.2008.4636089openalex-snapshot
STAMP: Stanford Transactional Applications for Multi-Processing
inferredcites →https://doi.org/10.1109/isca.1993.698569openalex-snapshot
Transactional Memory: Architectural Support For Lock-free Data Structures
inferredcites →https://doi.org/10.1109/isca.2004.1310767openalex-snapshot
Transactional memory coherence and consistency
inferredcites →https://doi.org/10.1109/isca.2006.9openalex-snapshot
Architectural Semantics for Practical Transactional Memory
inferredcites →https://doi.org/10.1145/1028176.1006711openalex-snapshot
Transactional Memory Coherence and Consistency
inferredcites →https://doi.org/10.1145/1150019.1136491openalex-snapshot
Architectural Semantics for Practical Transactional Memory
inferredcites →https://doi.org/10.1145/1250662.1250673openalex-snapshot
An effective hybrid transactional memory system with strong isolation guarantees
inferredcites →https://doi.org/10.1145/1250662.1250674openalex-snapshot
Performance pathologies in hardware transactional memory
inferredcites →https://doi.org/10.1145/1508244.1508263openalex-snapshot
Early experience with a commercial hardware transactional memory implementation
inferredcites →https://doi.org/10.1145/1542275.1542298openalex-snapshot
QuakeTM
inferredcites →https://doi.org/10.1145/165123.165164openalex-snapshot
Transactional memory
inferredcites →https://doi.org/10.1145/1755913.1755918openalex-snapshot
Evaluation of AMD's advanced synchronization facility within a complete transactional memory stack
inferredcites →https://doi.org/10.1145/1810479.1810537openalex-snapshot
Simplifying concurrent algorithms by exploiting hardware transactional memory
inferredcites →https://doi.org/10.1145/359863.359878openalex-snapshot
Concurrent reading and writing
inferredcites →https://doi.org/10.1145/99163.99185openalex-snapshot
A methodology for implementing highly concurrent data structures
inferredcites →https://doi.org/10.1145/99164.99185openalex-snapshot
A methodology for implementing highly concurrent data structures
inferredcites →https://doi.org/10.1145/996841.996848openalex-snapshot
Scalable lock-free dynamic memory allocation
inferredcites →https://doi.org/10.1145/996893.996848openalex-snapshot
Scalable lock-free dynamic memory allocation

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/978-1-4939-2092-1_27openalex-snapshot
Hardware Approaches to Transactional Memory in Chip Multiprocessors
inferred← citeshttps://doi.org/10.1007/978-3-319-14720-8_6openalex-snapshot
Conflict Detection in Hardware Transactional Memory
inferred← citeshttps://doi.org/10.1007/978-3-319-25703-7_6openalex-snapshot
Atomicity*
inferred← citeshttps://doi.org/10.1007/978-3-642-40047-6_22openalex-snapshot
VGTS: Variable Granularity Transactional Snoop
inferred← citeshttps://doi.org/10.1007/s00607-013-0375-4openalex-snapshot
TurboLock: increasing associativity of lock table in transactional memory
inferred← citeshttps://doi.org/10.1007/s11227-014-1138-5openalex-snapshot
Weighted adaptive concurrency control for software transactional memory
inferred← citeshttps://doi.org/10.1016/j.future.2013.06.017openalex-snapshot
Efficient execution of speculative threads and transactions with hardware transactional memory
inferred← citeshttps://doi.org/10.1016/j.jpdc.2012.09.015openalex-snapshot
Software transactional memories for Scala
inferred← citeshttps://doi.org/10.1016/j.parco.2015.12.002openalex-snapshot
Study of hardware transactional memory characteristics and serialization policies on Haswell
inferred← citeshttps://doi.org/10.1016/j.procs.2013.05.349openalex-snapshot
Implementation of Intel Restricted Transactional Memory ISA Extension in Simics
inferred← citeshttps://doi.org/10.1109/ccwc.2017.7868398openalex-snapshot
StAdHyTM: A Statically Adaptive Hybrid Transactional Memory: A scalability study on large parallel graphs
inferred← citeshttps://doi.org/10.1109/cjece.2014.2312217openalex-snapshot
Adaptive Snoop Granularity and Transactional Snoop Filtering in Hardware Transactional Memory
inferred← citeshttps://doi.org/10.1109/hipc.2013.6799100openalex-snapshot
HARP: Adaptive abort recurrence prediction for Hardware Transactional Memory
inferred← citeshttps://doi.org/10.1109/hipc.2013.6799126openalex-snapshot
Transaction scheduling using conflict avoidance and Contention Intensity
inferred← citeshttps://doi.org/10.1109/hpca.2014.6835951openalex-snapshot
Concurrent and consistent virtual machine introspection with hardware transactional memory
inferred← citeshttps://doi.org/10.1109/hpca.2018.00029openalex-snapshot
High-Performance GPU Transactional Memory via Eager Conflict Detection
inferred← citeshttps://doi.org/10.1109/icpads.2012.77openalex-snapshot
SeTM: Efficient Execution of Speculative Threads with Hardware Transactional Memory
inferred← citeshttps://doi.org/10.1109/ipdpsw.2013.113openalex-snapshot
Reducing False Transactional Conflicts with Speculative Sub-Blocking State -- An Empirical Study for ASF Transactional Memory System
inferred← citeshttps://doi.org/10.1109/isca.2018.00045openalex-snapshot
DHTM: Durable Hardware Transactional Memory
inferred← citeshttps://doi.org/10.1109/sbac-pad.2014.33openalex-snapshot
Multi-dimensional Evaluation of Haswell's Transactional Memory Performance
inferred← citeshttps://doi.org/10.1109/tc.2013.190openalex-snapshot
Software Support and Evaluation of Hardware Transactional Memory on Blue Gene/Q
inferred← citeshttps://doi.org/10.1109/tii.2025.3528582openalex-snapshot
HTM-PQC: Hardening Cryptography Keys Under the Trend of Post-Quantum Cryptography Migration on Industrial Internet
inferred← citeshttps://doi.org/10.1109/tmscs.2017.2773488openalex-snapshot
On Approximate Speculative Lock Elision
inferred← citeshttps://doi.org/10.1109/tpds.2018.2861712openalex-snapshot
The Case for Phase-Based Transactional Memory
inferred← citeshttps://doi.org/10.1109/tpds.2021.3085210openalex-snapshot
DeTraS: Delaying Stores for Friendly-Fire Mitigation in Hardware Transactional Memory
inferred← citeshttps://doi.org/10.1109/trustcom.2013.114openalex-snapshot
TxSnoop: Power-Aware Transactional Snoop
inferred← citeshttps://doi.org/10.1145/2155620.2155655openalex-snapshot
Hardware transactional memory for GPU architectures
inferred← citeshttps://doi.org/10.1145/2312005.2312014openalex-snapshot
Delegation and nesting in best-effort hardware transactional memory
inferred← citeshttps://doi.org/10.1145/2370816.2370836openalex-snapshot
Evaluation of Blue Gene/Q hardware support for transactional memories
inferred← citeshttps://doi.org/10.1145/2451116.2451136openalex-snapshot
DeAliaser
inferred← citeshttps://doi.org/10.1145/2451116.2451173openalex-snapshot
Wait-n-GoTM
inferred← citeshttps://doi.org/10.1145/2482767.2482773openalex-snapshot
Fault tolerance for multi-threaded applications by leveraging hardware transactional memory
inferred← citeshttps://doi.org/10.1145/2486159.2486165openalex-snapshot
Between all and nothing - versatile aborts in hardware transactional memory
inferred← citeshttps://doi.org/10.1145/2490301.2451136openalex-snapshot
DeAliaser
inferred← citeshttps://doi.org/10.1145/2490301.2451173openalex-snapshot
Wait-n-GoTM
inferred← citeshttps://doi.org/10.1145/2499368.2451136openalex-snapshot
DeAliaser
inferred← citeshttps://doi.org/10.1145/2499368.2451173openalex-snapshot
Wait-n-GoTM
inferred← citeshttps://doi.org/10.1145/2500727.2500745openalex-snapshot
Opportunities and pitfalls of multi-core scaling using hardware transaction memory
inferred← citeshttps://doi.org/10.1145/2541228.2555299openalex-snapshot
Techniques to improve performance in requester-wins hardware transactional memory
inferred← citeshttps://doi.org/10.1145/2592798.2592820openalex-snapshot
Algorithmic improvements for fast concurrent Cuckoo hashing
inferred← citeshttps://doi.org/10.1145/2688904openalex-snapshot
Transactional Read-Modify-Write Without Aborts
inferred← citeshttps://doi.org/10.1145/2755573.2755577openalex-snapshot
Conflict Reduction in Hardware Transactions Using Advisory Locks
inferred← citeshttps://doi.org/10.1145/2769458.2769462openalex-snapshot
Experiments with Hardware-based Transactional Memory in Parallel Simulation
inferred← citeshttps://doi.org/10.1145/3079079.3079094openalex-snapshot
Revisiting phased transactional memory
inferred← citeshttps://doi.org/10.1145/3132402.3132442openalex-snapshot
DyAdHyTM
inferred← citeshttps://doi.org/10.1145/3243176.3243186openalex-snapshot
Transactional pre-abort handlers in hardware transactional memory
inferred← citeshttps://doi.org/10.1145/3418055openalex-snapshot
GEVO
inferred← citeshttps://doi.org/10.1145/3503221.3508410openalex-snapshot
PathCAS
inferred← citeshttps://doi.org/10.14288/1.0167110openalex-snapshot
GPU computing architecture for irregular parallelism
inferred← citeshttps://doi.org/10.14778/2809974.2809990openalex-snapshot
To lock, swap, or elide
inferred← citeshttps://doi.org/10.15480/882.1240openalex-snapshot
Cloned Transactions : A New Execution Concept for Transactional Memory
inferred← citeshttps://doi.org/10.25046/aj050338openalex-snapshot
Based on Reconfiguring the Supercomputers Runtime Environment New Security Methods
inferred← citeshttps://doi.org/10.47749/t/unicamp.2015.949473openalex-snapshot
Scheduling and serialization techniques for transactional memories
inferred← citeshttps://doi.org/10.47749/t/unicamp.2020.1149098openalex-snapshot
Improving hardware/software transactional memory codesign
inferred← citeshttps://doi.org/10.48550/arxiv.2004.08140openalex-snapshot
GEVO: GPU Code Optimization using Evolutionary Computation
inferred← citeshttps://doi.org/10.5821/dissertation-2117-104207openalex-snapshot
A multicore emulator with a profiling infrastructure for transactional memory on FPGA
inferred← citeshttps://doi.org/10.5821/dissertation-2117-94562openalex-snapshot
Architectural support for high-performing hardware transactional memory systems
inferred← citeshttps://doi.org/10.5821/dissertation-2117-95386openalex-snapshot
Techniques to improve concurrency in hardware transactional memory
Editorial review for independent work. ICSAC — the Institute for Complexity Science and Advanced Computing — runs a structured editorial panel for researchers publishing outside journals, and publishes on CiteStamp rails. Submission is free and goes through ORCID: icsacinstitute.org/submit.