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Architectural Semantics for Practical Transactional Memory
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/11561927_26openalex-snapshot
Adaptive Software Transactional Memory
inferredcites →https://doi.org/10.1007/978-3-540-24851-4_24openalex-snapshot
Transactional Monitors for Concurrent Objects
inferredcites →https://doi.org/10.1016/j.scico.2005.03.005openalex-snapshot
Exceptions and side-effects in atomic blocks
inferredcites →https://doi.org/10.1109/hpca.2006.1598129openalex-snapshot
ReViveI/O: Efficient Handling of I/O in Highly-Available Rollback-Recovery Servers
inferredcites →https://doi.org/10.1109/hpca.2006.1598134openalex-snapshot
LogTM: Log-based Transactional Memory
inferredcites →https://doi.org/10.1109/hpca.2006.1598135openalex-snapshot
The Common Case Transactional Behavior of Multithreaded Programs
inferredcites →https://doi.org/10.1109/isca.1993.698569openalex-snapshot
Transactional Memory: Architectural Support For Lock-free Data Structures
inferredcites →https://doi.org/10.1109/isca.1995.524546openalex-snapshot
The SPLASH-2 programs: characterization and methodological considerations
inferredcites →https://doi.org/10.1109/isca.2004.1310767openalex-snapshot
Transactional memory coherence and consistency
inferredcites →https://doi.org/10.1109/isca.2005.54openalex-snapshot
Virtualizing Transactional Memory
inferredcites →https://doi.org/10.1109/pact.2005.11openalex-snapshot
Characterization of TCC on chip-multiprocessors
inferredcites →https://doi.org/10.1145/1065944.1065952openalex-snapshot
Composable memory transactions
inferredcites →https://doi.org/10.1145/1133981.1133985openalex-snapshot
Compiler and runtime support for efficient software transactional memory
inferredcites →https://doi.org/10.1145/339647.339650openalex-snapshot
A scalable approach to thread-level speculation
inferredcites →https://doi.org/10.1145/605397.605417openalex-snapshot
Enhancing software reliability with speculative threads
inferredcites →https://doi.org/10.1145/605398.605399openalex-snapshot
Transactional lock-free execution of lock-based programs
inferredcites →https://doi.org/10.1145/872035.872048openalex-snapshot
Software transactional memory for dynamic-sized data structures
inferredcites →https://doi.org/10.1145/949305.949340openalex-snapshot
Language support for lightweight transactions
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-3-031-01719-3_2openalex-snapshot
Programming Transactional Memory
inferred← citeshttps://doi.org/10.1007/978-3-540-69303-1_4openalex-snapshot
Transactional Memory and OpenMP
inferred← citeshttps://doi.org/10.1007/s10766-012-0210-0openalex-snapshot
Removal of Conflicts in Hardware Transactional Memory Systems
inferred← citeshttps://doi.org/10.1016/j.scico.2006.05.006openalex-snapshot
Executing Java programs with transactional memory
inferred← citeshttps://doi.org/10.1109/ancs.2015.7110117openalex-snapshot
Blueswitch: enabling provably consistent configuration of network switches
inferred← citeshttps://doi.org/10.1109/candar.2016.0026openalex-snapshot
A Concurrency Control in Hardware Transactional Memory Considering Execution Path Variation
inferred← citeshttps://doi.org/10.1109/cgo.2007.4openalex-snapshot
Code Generation and Optimization for Transactional Memory Constructs in an Unmanaged Language
inferred← citeshttps://doi.org/10.1109/hpca56546.2023.10071113openalex-snapshot
Safety Hints for HTM Capacity Abort Mitigation
inferred← citeshttps://doi.org/10.1109/icecs.2018.8618020openalex-snapshot
Isolation-Safe Speculative Access Control for Hardware Transactional Memory
inferred← citeshttps://doi.org/10.1109/iciecs.2009.5364966openalex-snapshot
Hardware Transactional Memory in Multicore Processors
inferred← citeshttps://doi.org/10.1109/icpp.2009.52openalex-snapshot
DTM: Decoupled Hardware Transactional Memory to Support Unbounded Transaction and Operating System
inferred← citeshttps://doi.org/10.1109/icsamos.2010.5642062openalex-snapshot
LV∗: A low complexity lazy versioning HTM infrastructure
inferred← citeshttps://doi.org/10.1109/iiswc.2010.5649529openalex-snapshot
Analysis on semantic transactional memory footprint for hardware transactional memory
inferred← citeshttps://doi.org/10.1109/ipdps.2007.370679openalex-snapshot
On the Role of Deterministic Fine-Grain Data Synchronization for Scientific Applications: A Revisit in the Emerging Many-Core Era
inferred← citeshttps://doi.org/10.1109/ipdps.2007.370680openalex-snapshot
On the Role of Deterministic Fine-Grain Data Synchronization for Scientific Applications: A Revisit in the Emerging Many-Core Era
inferred← citeshttps://doi.org/10.1109/ipdps.2008.4536249openalex-snapshot
Intermediate checkpointing with conflicting access prediction in transactional memory systems
inferred← citeshttps://doi.org/10.1109/isca.2008.26openalex-snapshot
Rerun: Exploiting Episodes for Lightweight Memory Race Recording
inferred← citeshttps://doi.org/10.1109/isca.2008.34openalex-snapshot
Using Hardware Memory Protection to Build a High-Performance, Strongly-Atomic Hybrid Transactional Memory
inferred← citeshttps://doi.org/10.1109/ispass.2008.4510738openalex-snapshot
An Analysis of I/O And Syscalls In Critical Sections And Their Implications For Transactional Memory
inferred← citeshttps://doi.org/10.1109/micro.2006.9openalex-snapshot
Architectural Support for Software Transactional Memory
inferred← citeshttps://doi.org/10.1109/micro.2008.4771794openalex-snapshot
Notary: Hardware techniques to enhance signatures
inferred← citeshttps://doi.org/10.1109/micro.2008.4771795openalex-snapshot
Dependence-aware transactional memory for increased concurrency
inferred← citeshttps://doi.org/10.1109/micro.2010.40openalex-snapshot
ASF: AMD64 Extension for Lock-Free Data Structures and Transactional Memory
inferred← citeshttps://doi.org/10.1109/micro.2012.12openalex-snapshot
Transactional Memory Architecture and Implementation for IBM System Z
inferred← citeshttps://doi.org/10.1109/micro.2018.00026openalex-snapshot
Harmonizing Speculative and Non-Speculative Execution in Architectures for Ordered Parallelism
inferred← citeshttps://doi.org/10.1109/mm.2007.26openalex-snapshot
Transactional Memory: The Hardware-Software Interface
inferred← citeshttps://doi.org/10.1109/mm.2008.10openalex-snapshot
MetaTM/TxLinux: Transactional Memory for an Operating System
inferred← citeshttps://doi.org/10.1109/mm.2016.48openalex-snapshot
2015 Maurice Wilkes Award Given to Christos Kozyrakis
inferred← citeshttps://doi.org/10.1109/pact.2007.4336227openalex-snapshot
The OpenTM Transactional Application Programming Interface
inferred← citeshttps://doi.org/10.1109/pact.2007.4336228openalex-snapshot
A Study of a Transactional Parallel Routing Algorithm
inferred← citeshttps://doi.org/10.1109/sbac-pad.2011.18openalex-snapshot
Classification and Elimination of Conflicts in Hardware Transactional Memory Systems
inferred← citeshttps://doi.org/10.1109/sbac-pad.2012.24openalex-snapshot
Integrating Dataflow Abstractions into the Shared Memory Model
inferred← citeshttps://doi.org/10.1109/sbac-pad.2013.9openalex-snapshot
Dealing with Reduction Operations Using Transactional Memory
inferred← citeshttps://doi.org/10.1109/tc.2013.190openalex-snapshot
Software Support and Evaluation of Hardware Transactional Memory on Blue Gene/Q
inferred← citeshttps://doi.org/10.1109/tpds.2013.262openalex-snapshot
ZEBRA: Data-Centric Contention Management in Hardware Transactional Memory
inferred← citeshttps://doi.org/10.1145/1133255.1133983openalex-snapshot
The Atomos transactional programming language
inferred← citeshttps://doi.org/10.1145/1133981.1133983openalex-snapshot
The Atomos transactional programming language
inferred← citeshttps://doi.org/10.1145/1168857.1168902openalex-snapshot
Supporting nested transactional memory in logTM
inferred← citeshttps://doi.org/10.1145/1168857.1168903openalex-snapshot
Tradeoffs in transactional memory virtualization
inferred← citeshttps://doi.org/10.1145/1168917.1168902openalex-snapshot
Supporting nested transactional memory in logTM
inferred← citeshttps://doi.org/10.1145/1168917.1168903openalex-snapshot
Tradeoffs in transactional memory virtualization
inferred← citeshttps://doi.org/10.1145/1168918.1168902openalex-snapshot
Supporting nested transactional memory in logTM
inferred← citeshttps://doi.org/10.1145/1168918.1168903openalex-snapshot
Tradeoffs in transactional memory virtualization
inferred← citeshttps://doi.org/10.1145/1168919.1168902openalex-snapshot
Supporting nested transactional memory in logTM
inferred← citeshttps://doi.org/10.1145/1168919.1168903openalex-snapshot
Tradeoffs in transactional memory virtualization
inferred← citeshttps://doi.org/10.1145/1178597.1178609openalex-snapshot
What do high-level memory models mean for transactions?
inferred← citeshttps://doi.org/10.1145/1178597.1178610openalex-snapshot
Memory models for open-nested transactions
inferred← citeshttps://doi.org/10.1145/1178597.1178611openalex-snapshot
Atomicity via source-to-source translation
inferred← citeshttps://doi.org/10.1145/1229428.1229441openalex-snapshot
Transactional collection classes
inferred← citeshttps://doi.org/10.1145/1229428.1229442openalex-snapshot
Open nesting in software transactional memory
inferred← citeshttps://doi.org/10.1145/1250662.1250673openalex-snapshot
An effective hybrid transactional memory system with strong isolation guarantees
inferred← citeshttps://doi.org/10.1145/1250662.1250674openalex-snapshot
Performance pathologies in hardware transactional memory
inferred← citeshttps://doi.org/10.1145/1250734.1250744openalex-snapshot
Enforcing isolation and ordering in STM
inferred← citeshttps://doi.org/10.1145/1254810.1254814openalex-snapshot
Speculative optimization using hardware-monitored guarded regions for java virtual machines
inferred← citeshttps://doi.org/10.1145/1273440.1250673openalex-snapshot
An effective hybrid transactional memory system with strong isolation guarantees
inferred← citeshttps://doi.org/10.1145/1273440.1250674openalex-snapshot
Performance pathologies in hardware transactional memory
inferred← citeshttps://doi.org/10.1145/1273442.1250744openalex-snapshot
Enforcing isolation and ordering in STM
inferred← citeshttps://doi.org/10.1145/1297027.1297080openalex-snapshot
The transactional memory / garbage collection analogy
inferred← citeshttps://doi.org/10.1145/1297105.1297080openalex-snapshot
The transactional memory / garbage collection analogy
inferred← citeshttps://doi.org/10.1145/1327171.1327181openalex-snapshot
Multithreaded software transactional memory and OpenMP
inferred← citeshttps://doi.org/10.1145/1345206.1345261openalex-snapshot
Safer open-nested transactions through ownership
inferred← citeshttps://doi.org/10.1145/1360443.1360458openalex-snapshot
Distributed computing and the multicore revolution
inferred← citeshttps://doi.org/10.1145/1378533.1378553openalex-snapshot
Safe open-nested transactions through ownership
inferred← citeshttps://doi.org/10.1145/1378533.1378564openalex-snapshot
Adaptive transaction scheduling for transactional memory systems
inferred← citeshttps://doi.org/10.1145/1394608.1382132openalex-snapshot
Using Hardware Memory Protection to Build a High-Performance, Strongly-Atomic Hybrid Transactional Memory
inferred← citeshttps://doi.org/10.1145/1504176.1504200openalex-snapshot
Safe open-nested transactions through ownership
inferred← citeshttps://doi.org/10.1145/1508244.1508262openalex-snapshot
Maximum benefit from a minimal HTM
inferred← citeshttps://doi.org/10.1145/1508284.1508262openalex-snapshot
Maximum benefit from a minimal HTM
inferred← citeshttps://doi.org/10.1145/1534530.1534533openalex-snapshot
Transactifying Apache's cache module
inferred← citeshttps://doi.org/10.1145/1542275.1542297openalex-snapshot
Fast memory snapshot for concurrent programmingwithout synchronization
inferred← citeshttps://doi.org/10.1145/1594835.1504200openalex-snapshot
Safe open-nested transactions through ownership
inferred← citeshttps://doi.org/10.1145/1669112.1669133openalex-snapshot
Proactive transaction scheduling for contention management
inferred← citeshttps://doi.org/10.1145/1669112.1669159openalex-snapshot
Using a configurable processor generator for computer architecture prototyping
inferred← citeshttps://doi.org/10.1145/1739025.1739037openalex-snapshot
From lock to correct and efficient software transactional memory
inferred← citeshttps://doi.org/10.1145/1810479.1810528openalex-snapshot
Implementing and evaluating nested parallel transactions in software transactional memory
inferred← citeshttps://doi.org/10.1145/2086696.2086710openalex-snapshot
Hardware transactional memory with software-defined conflicts
inferred← citeshttps://doi.org/10.1145/2400682.2400701openalex-snapshot
An integrated pseudo-associativity and relaxed-order approach to hardware transactional memory
inferred← citeshttps://doi.org/10.1145/2485922.2485942openalex-snapshot
Robust architectural support for transactional memory in the power architecture
inferred← citeshttps://doi.org/10.1145/2508148.2485942openalex-snapshot
Robust architectural support for transactional memory in the power architecture
inferred← citeshttps://doi.org/10.1145/2528521.1508262openalex-snapshot
Maximum benefit from a minimal HTM
inferred← citeshttps://doi.org/10.1145/2684464.2684467openalex-snapshot
On Reducing False Conflicts in Distributed Transactional Data Structures
inferred← citeshttps://doi.org/10.1145/3243176.3243186openalex-snapshot
Transactional pre-abort handlers in hardware transactional memory
inferred← citeshttps://doi.org/10.1587/transinf.2016pap0006openalex-snapshot
A Waiting Mechanism with Conflict Prediction on Hardware Transactional Memory
inferred← citeshttps://doi.org/10.2200/s00070ed1v01y200611cac002openalex-snapshot
Transactional Memory
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Transactional Memory, 2nd edition
inferred← citeshttps://doi.org/10.47749/t/unicamp.2013.918322openalex-snapshot
Análise e estudo de desempenho e consumo de energia de memórias transacionais em software
inferred← citeshttps://doi.org/10.5821/dissertation-2117-94452openalex-snapshot
Programming, debugging, profiling and optimizing transactional memory programs
inferred← citeshttps://doi.org/10.5821/dissertation-2117-94562openalex-snapshot
Architectural support for high-performing hardware transactional memory systems
inferred← citeshttps://doi.org/10.5821/dissertation-2117-94989openalex-snapshot
Towards lightweight and high-performance hardware transactional memory
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Extending the applicability of deterministic multithreading
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