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Leveraging Heterogeneity in DRAM Main Memories to Accelerate Critical Word Access
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
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Simics: A full system simulation platform
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An RLDRAM II Implementation of a 10Gbps Shared Packet Buffer for Network Processing
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MLP aware heterogeneous memory system
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Hybrid memory cube (HMC)
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A performance comparison of contemporary DRAM architectures
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BOOM: Enabling mobile memory based low-power server DIMMs
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Towards energy-proportional datacenter memory with mobile DRAM
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Synthesizing memory-level parallelism aware miniature clones for SPEC CPU2006 and ImplantBench workloads
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A 1.2V 30nm 1.6Gb/s/pin 4Gb LPDDR3 SDRAM with input skew calibration and enhanced control scheme
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Understanding the Energy Consumption of Dynamic Random Access Memories
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CHOP: Integrating DRAM Caches for CMP Server Platforms
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Server Engineering Insights for Large-Scale Online Services
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Exploring Phase Change Memory and 3D Die-Stacking for Power/Thermal Friendly, Fast and Durable Memory Architectures
inferredcites →https://doi.org/10.1109/sc.2010.50openalex-snapshot
Simple but Effective Heterogeneous Main Memory with On-Chip Memory Controller Support
inferredcites →https://doi.org/10.1109/tc.2004.27openalex-snapshot
Design and optimization of large size and low overhead off-chip caches
inferredcites →https://doi.org/10.1145/1555754.1555758openalex-snapshot
Architecting phase change memory as a scalable dram alternative
inferredcites →https://doi.org/10.1145/1555754.1555759openalex-snapshot
A durable and energy efficient main memory using phase change memory technology
inferredcites →https://doi.org/10.1145/1555754.1555760openalex-snapshot
Scalable high performance main memory system using phase-change memory technology
inferredcites →https://doi.org/10.1145/1654059.1654102openalex-snapshot
Future scaling of processor-memory interfaces
inferredcites →https://doi.org/10.1145/1815961.1815967openalex-snapshot
Energy-performance tradeoffs in processor architecture and circuit design
inferredcites →https://doi.org/10.1145/1815961.1815983openalex-snapshot
Rethinking DRAM design and organization for energy-constrained multi-cores
inferredcites →https://doi.org/10.1145/1816038.1815967openalex-snapshot
Energy-performance tradeoffs in processor architecture and circuit design
inferredcites →https://doi.org/10.1145/1995896.1995911openalex-snapshot
Page placement in hybrid memory systems
inferredcites →https://doi.org/10.1145/2155620.2155673openalex-snapshot
Efficiently enabling conventional block sizes for very large die-stacked DRAM caches
inferredcites →https://doi.org/10.1145/2366231.2337164openalex-snapshot
Towards energy-proportional datacenter memory with mobile DRAM
inferredcites →https://doi.org/10.1145/300979.300998openalex-snapshot
A performance comparison of contemporary DRAM architectures
inferredcites →https://doi.org/10.1177/109434209100500306openalex-snapshot
The NAS Parallel Benchmarks
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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Modeling and Analyzing of 3D DRAM as L3 Cache Based on DRAMSim2
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Reliability Issues in Flash-Memory-Based Solid-State Drives: Experimental Analysis, Mitigation, Recovery
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A Survey of Phase Change Memory Systems
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Survey on memory management techniques in heterogeneous computing systems
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Energy Reduction Through Memory Aware Real-Time Scheduling on Virtual Machine in Multi-Cores Server
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High-Performance and Power-Saving Mechanism for Page Activations Based on Full Independent DRAM Sub-Arrays in Multi-Core Systems
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A Highly Parallel DRAM Architecture to Mitigate Large Access Latency and Improve Energy Efficiency of Modern DRAM Systems
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Utility-Based Hybrid Memory Management
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Characterizing Application Memory Error Vulnerability to Optimize Datacenter Cost via Heterogeneous-Reliability Memory
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The runahead network-on-chip
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ChargeCache: Reducing DRAM latency by exploiting row access locality
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Increasing cache capacity via critical-words-only cache
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MOCA: Memory Object Classification and Allocation in Heterogeneous Memory Systems
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MLC PCM main memory with accelerated read
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SALAD: Achieving Symmetric Access Latency with Asymmetric DRAM Architecture
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Object Placement for High Bandwidth Memory Augmented with High Capacity Memory
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Unaligned Burst-Aware Memory Subsystem
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