On the public citation graph
CAMEO: A Two-Level Memory Organization with Capacity of Main Memory and Flexibility of Hardware-Managed Cache
0 signed · 161 inferred · view as graph
Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.
Is this your work? Sign in with ORCID and put your name on the
claims that are yours.
Reference health. See whether every reference in this work resolves to a
known work and none has been retracted — and get a dated CiteStamped
badge you can embed.
What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1109/hpca.2010.5416642openalex-snapshot
CHOP: Adaptive filter-based DRAM caching for CMP server platforms
inferredcites →https://doi.org/10.1109/iccd.2007.4601880openalex-snapshot
Exploring DRAM cache architectures for CMP server platforms
inferredcites →https://doi.org/10.1109/isca.1994.288163openalex-snapshot
Tradeoffs in two-level on-chip caching
inferredcites →https://doi.org/10.1109/micro.2012.11openalex-snapshot
Leveraging Heterogeneity in DRAM Main Memories to Accelerate Critical Word Access
inferredcites →https://doi.org/10.1109/micro.2012.30openalex-snapshot
Fundamental Latency Trade-off in Architecting DRAM Caches: Outperforming Impractical SRAM-Tags with a Simple and Practical Design
inferredcites →https://doi.org/10.1109/micro.2012.31openalex-snapshot
A Mostly-Clean DRAM Cache for Effective Hit Speculation and Self-Balancing Dispatch
inferredcites →https://doi.org/10.1109/sc.2010.50openalex-snapshot
Simple but Effective Heterogeneous Main Memory with On-Chip Memory Controller Support
inferredcites →https://doi.org/10.1145/1054943.1054944openalex-snapshot
A case for multi-level main memory
inferredcites →https://doi.org/10.1145/1133572.1133573openalex-snapshot
When physical is not real enough
inferredcites →https://doi.org/10.1145/169627.169699openalex-snapshot
An empirical comparison of the Kendall Square Research KSR-1 and Stanford DASH multiprocessors
inferredcites →https://doi.org/10.1145/1854273.1854333openalex-snapshot
Using dead blocks as a virtual victim cache
inferredcites →https://doi.org/10.1145/2155620.2155673openalex-snapshot
Efficiently enabling conventional block sizes for very large die-stacked DRAM caches
inferredcites →https://doi.org/10.1145/2485922.2485957openalex-snapshot
Die-stacked DRAM caches for servers
inferredcites →https://doi.org/10.1145/2508148.2485957openalex-snapshot
Die-stacked DRAM caches for servers
inferredcites →https://doi.org/10.1145/291006.291032openalex-snapshot
Hardware-software trade-offs in a direct Rambus implementation of the RAMpage memory hierarchy
inferredcites →https://doi.org/10.1145/291069.291032openalex-snapshot
Hardware-software trade-offs in a direct Rambus implementation of the RAMpage memory hierarchy
inferredcites →https://doi.org/10.1145/331532.331570openalex-snapshot
Performance experiences on Sun's Wildfire prototype
inferredcites →https://doi.org/10.1147/rd.524.0465openalex-snapshot
Phase-change random access memory: A scalable technology
inferredcites →https://doi.org/10.2200/s00381ed1v01y201109cac018openalex-snapshot
Phase Change Memory: From Devices to Systems
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-3-319-54999-6_10openalex-snapshot
HBM-Resident Prefetching for Heterogeneous Memory System
inferred← citeshttps://doi.org/10.1007/978-3-319-72971-8_5openalex-snapshot
Modeling Large Compute Nodes with Heterogeneous Memories with Cache-Aware Roofline Model
inferred← citeshttps://doi.org/10.1007/978-3-662-49283-3_1openalex-snapshot
Modeling and Analyzing of 3D DRAM as L3 Cache Based on DRAMSim2
inferred← citeshttps://doi.org/10.1007/978-981-13-0599-3_9openalex-snapshot
Reliability Issues in Flash-Memory-Based Solid-State Drives: Experimental Analysis, Mitigation, Recovery
inferred← citeshttps://doi.org/10.1007/s11390-023-2561-yopenalex-snapshot
P3DC: Reducing DRAM Cache Hit Latency by Hybrid Mappings
inferred← citeshttps://doi.org/10.1007/s11432-016-0408-1openalex-snapshot
Toward multi-programmed workloads with different memory footprints: a self-adaptive last level cache scheduling scheme
inferred← citeshttps://doi.org/10.1007/s11704-017-6349-5openalex-snapshot
HSCS: a hybrid shared cache scheduling scheme for multiprogrammed workloads
inferred← citeshttps://doi.org/10.1016/j.future.2016.07.014openalex-snapshot
Composable architecture for rack scale big data computing
inferred← citeshttps://doi.org/10.1016/j.suscom.2020.100449openalex-snapshot
Line-Coalescing DRAM Cache
inferred← citeshttps://doi.org/10.1016/j.sysarc.2020.101886openalex-snapshot
Efficient Cache Resizing policy for DRAM-based LLCs in ChipMultiprocessors
inferred← citeshttps://doi.org/10.1080/02564602.2022.2127945openalex-snapshot
Challenges in Design, Data Placement, Migration and Power-Performance Trade-offs in DRAM-NVM-based Hybrid Memory Systems
inferred← citeshttps://doi.org/10.1109/access.2025.3648766openalex-snapshot
ProactivePIM: Accelerating Weight-Sharing Embedding Layer With PIM for Scalable Recommendation System
inferred← citeshttps://doi.org/10.1109/cahpc.2018.8645903openalex-snapshot
Phase-Based Data Placement Scheme for Heterogeneous Memory Systems
inferred← citeshttps://doi.org/10.1109/cluster.2017.130openalex-snapshot
Utility-Based Hybrid Memory Management
inferred← citeshttps://doi.org/10.1109/hpca.2015.7056027openalex-snapshot
Heterogeneous memory architectures: A HW/SW approach for mixing die-stacked and off-package memories
inferred← citeshttps://doi.org/10.1109/hpca.2016.7446068openalex-snapshot
Efficient footprint caching for Tagless DRAM Caches
inferred← citeshttps://doi.org/10.1109/hpca.2017.20openalex-snapshot
SILC-FM: Subblocked InterLeaved Cache-Like Flat Memory Organization
inferred← citeshttps://doi.org/10.1109/hpca.2017.39openalex-snapshot
MemPod: A Clustered Architecture for Efficient and Scalable Migration in Flat Address Space Multi-level Memories
inferred← citeshttps://doi.org/10.1109/hpca.2018.00022openalex-snapshot
ProFess: A Probabilistic Hybrid Main Memory Management Framework for High Performance and Fairness
inferred← citeshttps://doi.org/10.1109/hpca.2018.00056openalex-snapshot
Reliability-Aware Data Placement for Heterogeneous Memory Architecture
inferred← citeshttps://doi.org/10.1109/hpca.2019.00012openalex-snapshot
PageSeer: Using Page Walks to Trigger Page Swaps in Hybrid Memory Systems
inferred← citeshttps://doi.org/10.1109/hpca47549.2020.00059openalex-snapshot
Hybrid2: Combining Caching and Migration in Hybrid Memory Systems
inferred← citeshttps://doi.org/10.1109/hpca51647.2021.00022openalex-snapshot
Stealth-Persist: Architectural Support for Persistent Applications in Hybrid Memory Systems
inferred← citeshttps://doi.org/10.1109/hpca56546.2023.10071089openalex-snapshot
Dalorex: A Data-Local Program Execution and Architecture for Memory-bound Applications
inferred← citeshttps://doi.org/10.1109/hpca56546.2023.10071115openalex-snapshot
Baryon: Efficient Hybrid Memory Management with Compression and Sub-Blocking
inferred← citeshttps://doi.org/10.1109/hpca57654.2024.00021openalex-snapshot
Bandwidth-Effective DRAM Cache for GPU s with Storage-Class Memory
inferred← citeshttps://doi.org/10.1109/hpca61900.2025.00062openalex-snapshot
Efficient Caching with A Tag-enhanced DRAM
inferred← citeshttps://doi.org/10.1109/hpcc/smartcity/dss.2018.00119openalex-snapshot
3D-DRAM Performance for Different OpenMP Scheduling Techniques in Multicore Systems
inferred← citeshttps://doi.org/10.1109/iccd.2016.7753270openalex-snapshot
Dynamic prefetcher reconfiguration for diverse memory architectures
inferred← citeshttps://doi.org/10.1109/iccd.2018.00054openalex-snapshot
Puzzle Memory: Multifractional Partitioned Heterogeneous Memory Scheme
inferred← citeshttps://doi.org/10.1109/iccd46524.2019.00055openalex-snapshot
TicToc: Enabling Bandwidth-Efficient DRAM Caching for Both Hits and Misses in Hybrid Memory Systems
inferred← citeshttps://doi.org/10.1109/iccd56317.2022.00015openalex-snapshot
Supporting Dynamic Translation Granularity for Hybrid Memory Systems
inferred← citeshttps://doi.org/10.1109/icce.2018.8326295openalex-snapshot
Bandwidth-aware DRAM page migration for heterogeneous mobile memory systems
inferred← citeshttps://doi.org/10.1109/icpp.2017.21openalex-snapshot
Efficient Data Sharing on Heterogeneous Systems
inferred← citeshttps://doi.org/10.1109/ipdps.2019.00101openalex-snapshot
LLC-Guided Data Migration in Hybrid Memory Systems
inferred← citeshttps://doi.org/10.1109/isca52012.2021.00059openalex-snapshot
SPACE: Locality-Aware Processing in Heterogeneous Memory for Personalized Recommendations
inferred← citeshttps://doi.org/10.1109/isca66397.2026.00046openalex-snapshot
LÆGIS: Pinpointing and Addressing Performance Overheads of GPU-Based Confidential Computing
inferred← citeshttps://doi.org/10.1109/ispass51385.2021.00036openalex-snapshot
A Case Against Hardware Managed DRAM Caches for NVRAM Based Systems
inferred← citeshttps://doi.org/10.1109/mascots.2017.23openalex-snapshot
SELF: A High Performance and Bandwidth Efficient Approach to Exploiting Die-Stacked DRAM as Part of Memory
inferred← citeshttps://doi.org/10.1109/mascots56607.2022.00023openalex-snapshot
Design and Simulation of Multi-tiered Heterogeneous Memory Architecture
inferred← citeshttps://doi.org/10.1109/mchpc51950.2020.00007openalex-snapshot
Performance Potential of Mixed Data Management Modes for Heterogeneous Memory Systems
inferred← citeshttps://doi.org/10.1109/mdat.2015.2463282openalex-snapshot
Overview of 3-D Architecture Design Opportunities and Techniques
inferred← citeshttps://doi.org/10.1109/micro.2016.7783738openalex-snapshot
CANDY: Enabling coherent DRAM caches for multi-node systems
inferred← citeshttps://doi.org/10.1109/micro.2018.00050openalex-snapshot
CHAMELEON: A Dynamically Reconfigurable Heterogeneous Memory System
inferred← citeshttps://doi.org/10.1109/micro20571.2012openalex-snapshot
2012 45th Annual IEEE/ACM International Symposium on Microarchitecture
inferred← citeshttps://doi.org/10.1109/micro61859.2024.00098openalex-snapshot
Blenda: Dynamically-Reconfigurable Stacked DRAM
inferred← citeshttps://doi.org/10.1109/micro61859.2024.00111openalex-snapshot
NeoMem: Hardware/Software Co-Design for CXL-Native Memory Tiering
inferred← citeshttps://doi.org/10.1109/micro61859.2024.00120openalex-snapshot
Stream-Based Data Placement for Near-Data Processing with Extended Memory
inferred← citeshttps://doi.org/10.1109/mm.2015.72openalex-snapshot
Designing Efficient Heterogeneous Memory Architectures
inferred← citeshttps://doi.org/10.1109/nas.2016.7549421openalex-snapshot
Soft2LM: Application Guided Heterogeneous Memory Management
inferred← citeshttps://doi.org/10.1109/nas.2018.8515694openalex-snapshot
MemBrain: Automated Application Guidance for Hybrid Memory Systems
inferred← citeshttps://doi.org/10.1109/pact65351.2025.00018openalex-snapshot
Exploring Memory Tiering Systems in the CXL Era via FPGA-based Emulation and Device-Side Management
inferred← citeshttps://doi.org/10.1109/pccc.2016.7820659openalex-snapshot
Small cache lookaside table for fast DRAM cache access
inferred← citeshttps://doi.org/10.1109/pccc.2018.8711335openalex-snapshot
A Cost-effective and Energy-efficient Architecture for Die-stacked DRAM/NVM Memory Systems
inferred← citeshttps://doi.org/10.1109/pdp2018.2018.00063openalex-snapshot
Utilizing Heterogeneous Memory Hierarchies in the PGAS Model
inferred← citeshttps://doi.org/10.1109/sbac-pad.2015.34openalex-snapshot
i-MIRROR: A Software Managed Die-Stacked DRAM-Based Memory Subsystem
inferred← citeshttps://doi.org/10.1109/sc.2016.75openalex-snapshot
DCA: A DRAM-cache-Aware DRAM Controller
inferred← citeshttps://doi.org/10.1109/sc41406.2024.00017openalex-snapshot
Hydrogen: Contention-Aware Hybrid Memory for Heterogeneous CPU-GPU Architectures
inferred← citeshttps://doi.org/10.1109/tc.2019.2906597openalex-snapshot
An Analytical Model for Performance and Lifetime Estimation of Hybrid DRAM-NVM Main Memories
inferred← citeshttps://doi.org/10.1109/tc.2020.2964254openalex-snapshot
Joint Management of CPU and NVDIMM for Breaking Down the Great Memory Wall
inferred← citeshttps://doi.org/10.1109/tc.2020.3036686openalex-snapshot
Adaptive Page Migration Policy With Huge Pages in Tiered Memory Systems
inferred← citeshttps://doi.org/10.1109/tcad.2017.2666604openalex-snapshot
TSV-Based 3-D ICs: Design Methods and Tools
inferred← citeshttps://doi.org/10.1109/tcad.2019.2927528openalex-snapshot
Temperature-Aware DRAM Cache Management—Relaxing Thermal Constraints in 3-D Systems
inferred← citeshttps://doi.org/10.1109/tcad.2020.3012213openalex-snapshot
Hardware Memory Management for Future Mobile Hybrid Memory Systems
inferred← citeshttps://doi.org/10.1109/tcad.2022.3231836openalex-snapshot
RHPM: Using Relative Hotness to Guide Page Migration for Hybrid Memory Systems
inferred← citeshttps://doi.org/10.1109/tcad.2023.3333284openalex-snapshot
AdaptHM: A Fully Adaptive Data Migration Strategy for Hybrid Memory Systems
inferred← citeshttps://doi.org/10.1109/tcad.2024.3455237openalex-snapshot
Phoenix: A Dynamically Reconfigurable Hybrid Memory System Combining Caching and Migration
inferred← citeshttps://doi.org/10.1109/tetc.2018.2800721openalex-snapshot
Trade-off between Hit Rate and Hit Latency for Optimizing DRAM Cache
inferred← citeshttps://doi.org/10.1109/tpds.2015.2461155openalex-snapshot
A Survey Of Techniques for Architecting DRAM Caches
inferred← citeshttps://doi.org/10.1109/tpds.2018.2883056openalex-snapshot
Modeling Non-Uniform Memory Access on Large Compute Nodes with the Cache-Aware Roofline Model
inferred← citeshttps://doi.org/10.1109/tpds.2022.3227544openalex-snapshot
Exploring Memory Access Similarity to Improve Irregular Application Performance for Distributed Hybrid Memory Systems
inferred← citeshttps://doi.org/10.1109/vlsi-dat49148.2020.9196490openalex-snapshot
Intelligent Architectures for Intelligent Machines
inferred← citeshttps://doi.org/10.1145/2989081.2989089openalex-snapshot
Analytical Study on Bandwidth Efficiency of Heterogeneous Memory Systems
inferred← citeshttps://doi.org/10.1145/2989081.2989097openalex-snapshot
Challenges of Programming a System with Heterogeneous Memories and Heterogeneous Processors
inferred← citeshttps://doi.org/10.1145/2989081.2989113openalex-snapshot
Reliability and Performance Trade-off Study of Heterogeneous Memories
inferred← citeshttps://doi.org/10.1145/2989081.2989129openalex-snapshot
Prefetching as a Potentially Effective Technique for Hybrid Memory Optimization
inferred← citeshttps://doi.org/10.1145/3068460openalex-snapshot
Dirty-Block Tracking in a Direct-Mapped DRAM Cache with Self-Balancing Dispatch
inferred← citeshttps://doi.org/10.1145/3079079.3079089openalex-snapshot
Hardware/software cooperative caching for hybrid DRAM/NVM memory architectures
inferred← citeshttps://doi.org/10.1145/3079856.3080210openalex-snapshot
Rethinking TLB Designs in Virtualized Environments
inferred← citeshttps://doi.org/10.1145/3140659.3080210openalex-snapshot
Rethinking TLB Designs in Virtualized Environments
inferred← citeshttps://doi.org/10.1145/3176258.3176325openalex-snapshot
Secure, Consistent, and High-Performance Memory Snapshotting
inferred← citeshttps://doi.org/10.1145/3205289.3208064openalex-snapshot
A Case for Granularity Aware Page Migration
inferred← citeshttps://doi.org/10.1145/3240302.3240310openalex-snapshot
Design guidelines for high-performance SCM hierarchies
inferred← citeshttps://doi.org/10.1145/3297858.3304024openalex-snapshot
Nimble Page Management for Tiered Memory Systems
inferred← citeshttps://doi.org/10.1145/3310133openalex-snapshot
Supporting Superpages and Lightweight Page Migration in Hybrid Memory Systems
inferred← citeshttps://doi.org/10.1145/3338505openalex-snapshot
Morphable DRAM Cache Design for Hybrid Memory Systems
inferred← citeshttps://doi.org/10.1145/3357526.3357543openalex-snapshot
Page migration support for disaggregated non-volatile memories
inferred← citeshttps://doi.org/10.1145/3431803openalex-snapshot
Reliability-aware Garbage Collection for Hybrid HBM-DRAM Memories
inferred← citeshttps://doi.org/10.1145/3444750openalex-snapshot
Dynamically Adapting Page Migration Policies Based on Applications’ Memory Access Behaviors
inferred← citeshttps://doi.org/10.1145/3445814.3446745openalex-snapshot
KLOCs: kernel-level object contexts for heterogeneous memory systems
inferred← citeshttps://doi.org/10.1145/3494536openalex-snapshot
Software Hint-Driven Data Management for Hybrid Memory in Mobile Systems
inferred← citeshttps://doi.org/10.1145/3533855openalex-snapshot
Online Application Guidance for Heterogeneous Memory Systems
inferred← citeshttps://doi.org/10.1145/3600006.3613167openalex-snapshot
MEMTIS: Efficient Memory Tiering with Dynamic Page Classification and Page Size Determination
inferred← citeshttps://doi.org/10.1145/3650200.3656612openalex-snapshot
HMComp: Extending Near-Memory Capacity using Compression in Hybrid Memory
inferred← citeshttps://doi.org/10.1145/3656019.3689612openalex-snapshot
Trimma: Trimming Metadata Storage and Latency for Hybrid Memory Systems
inferred← citeshttps://doi.org/10.1145/3777549openalex-snapshot
Harnessing Page Access Frequency Distribution for Efficient Memory Tiering
inferred← citeshttps://doi.org/10.1145/3779212.3790203openalex-snapshot
PIPM: Partial and Incremental Page Migration for Multi-host CXL Disaggregated Shared Memory
inferred← citeshttps://doi.org/10.12794/metadc1505134openalex-snapshot
A Study on Flat-Address-Space Heterogeneous Memory Architectures
inferred← citeshttps://doi.org/10.12794/metadc1505199openalex-snapshot
Methodical Evaluation of Processing-in-Memory Alternatives
inferred← citeshttps://doi.org/10.12794/metadc1873542openalex-snapshot
Improving Memory Performance for Both High Performance Computing and Embedded/Edge Computing Systems
inferred← citeshttps://doi.org/10.1587/elex.14.20171002openalex-snapshot
Energy-efficient heterogeneous memory system for mobile platforms
inferred← citeshttps://doi.org/10.1587/transele.2021lhp0004openalex-snapshot
A Metadata Prefetching Mechanism for Hybrid Memory Architectures
inferred← citeshttps://doi.org/10.1631/fitee.1500352openalex-snapshot
Fine-grained checkpoint based on non-volatile memory
inferred← citeshttps://doi.org/10.2200/s00644ed1v01y201505cac031openalex-snapshot
Die-stacking Architecture
inferred← citeshttps://doi.org/10.23919/date51398.2021.9474073openalex-snapshot
Intelligent Architectures for Intelligent Computing Systems
inferred← citeshttps://doi.org/10.23919/date56975.2023.10137177openalex-snapshot
AGDM: An Adaptive Granularity Data Migration Strategy for Hybrid Memory Systems
inferred← citeshttps://doi.org/10.3390/electronics9122061openalex-snapshot
Polymorphic Memory: A Hybrid Approach for Utilizing On-Chip Memory in Manycore Systems
inferred← citeshttps://doi.org/10.48550/arxiv.1503.01416openalex-snapshot
Disaggregated and optically interconnected memory: when will it be cost effective?
inferred← citeshttps://doi.org/10.48550/arxiv.1704.02677openalex-snapshot
Banshee: Bandwidth-Efficient DRAM Caching Via Software/Hardware Cooperation
inferred← citeshttps://doi.org/10.48550/arxiv.1711.11427openalex-snapshot
Errors in Flash-Memory-Based Solid-State Drives: Analysis, Mitigation, and Recovery
inferred← citeshttps://doi.org/10.48550/arxiv.1804.11040openalex-snapshot
A Memory Controller with Row Buffer Locality Awareness for Hybrid Memory Systems
inferred← citeshttps://doi.org/10.48550/arxiv.1805.02819openalex-snapshot
Experimental Characterization, Optimization, and Recovery of Data Retention Errors in MLC NAND Flash Memory
inferred← citeshttps://doi.org/10.48550/arxiv.1808.04016openalex-snapshot
Architectural Techniques for Improving NAND Flash Memory Reliability
inferred← citeshttps://doi.org/10.48550/arxiv.1809.08828openalex-snapshot
Die-Stacked DRAM: Memory, Cache, or MemCache?
inferred← citeshttps://doi.org/10.5075/epfl-thesis-6631openalex-snapshot
Multi-Gigabyte On-Chip DRAM Caches for Servers
inferred← citeshttps://doi.org/10.5821/dissertation-2117-113684openalex-snapshot
Memory hierarchies for future HPC architectures
inferred← citeshttps://doi.org/10.5821/dissertation-2117-121194openalex-snapshot
Memory systems for high-performance computing: the capacity and reliability implications
inferred← citeshttps://doi.org/10.70675/9ceff097zac2dz4953zbc3aza17e497ce08bopenalex-snapshot
Optimisation des allocations de données pour des applications du Calcul Haute Performance sur une architecture à mémoires hétérogènes
inferred← citeshttps://doi.org/10.7282/t3-m0cq-tt95openalex-snapshot
Improving and complementing virtual memory using hardware techniques
inferred← citeshttps://doi.org/10.7282/t3xk8jzjopenalex-snapshot
A 3D-Stacked Architecture for Secure Memory Acquisition
Editorial review for independent work. ICSAC — the Institute for Complexity
Science and Advanced Computing — runs a structured editorial panel for researchers
publishing outside journals, and publishes on CiteStamp rails. Submission is free
and goes through ORCID: icsacinstitute.org/submit.