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Libra: Tailoring SIMD Execution Using Heterogeneous Hardware and Dynamic Configurability
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
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Exploiting ILP, TLP, and DLP with the polymorphous TRIPS architecture
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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Towards Transparent Dynamic Binary Translation from RISC-V to a CGRA
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Performance Evaluation of NPB and SPEC CPU2006 on Various SIMD Extensions
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A Study on L1 Data Cache Bypassing Methods for High-Performance GPUs
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Construction and exploitation of VLIW ASIPs with heterogeneous vector-widths
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Early miss prediction based periodic cache bypassing for high performance GPUs
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MIMD Programs Execution Support on SIMD Machines: A Holistic Survey
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Mixed-length SIMD code generation for VLIW architectures with multiple native vector-widths
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Coordinated static and dynamic cache bypassing for GPUs
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Software transparent dynamic binary translation for coarse-grain reconfigurable architectures
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Can lock-free and combining techniques co-exist?: a novel approach on concurrent queue
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Exploring the potential of heterogeneous von neumann/dataflow execution models
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Stream-based memory access specialization for general purpose processors
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R-Blocks: an Energy-Efficient, Flexible, and Programmable CGRA
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Exploiting Fine-Grain Ordered Parallelism in Dense Matrix Algorithms
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Breaking SIMD shackles with an exposed flexible microarchitecture and the access execute PDG
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