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R-Blocks: an Energy-Efficient, Flexible, and Programmable CGRA

https://doi.org/10.1145/3656642
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Outgoing claims: the papers this work cites, builds on, or argues with.

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VPR: a new packing, placement and routing tool for FPGA research
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Architecture and CAD for Deep-Submicron FPGAS
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Architecture of Computing Systems - ARCS 2017
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Versat, a Minimal Coarse-Grain Reconfigurable Array
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A Low-Energy Wide SIMD Architecture with Explicit Datapath
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Floating Point CGRA based Ultra-Low Power DSP Accelerator
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AEx: Automated High-Level Synthesis of Compiler Programmable Co-Processors
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HyCUBE: A 0.9V 26.4 MOPS/mW, 290 pJ/op, Power Efficient Accelerator for IoT Applications
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A Survey on Coarse-Grained Reconfigurable Architectures From a Performance Perspective
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2021 IEEE 3rd International Conference on Artificial Intelligence Circuits and Systems (AICAS)
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Integer-Only Approximated MFCC for Ultra-Low Power Audio NN Processing on Multi-Core MCUs
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CGRA-ME: A unified framework for CGRA modelling and exploration
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2016 IEEE 27th International Conference on Application-specific Systems, Architectures and Processors (ASAP)
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2021 IEEE 32nd International Conference on Application-specific Systems, Architectures and Processors (ASAP)
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OpenCGRA: Democratizing Coarse-Grained Reconfigurable Arrays
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Scalable EEG seizure detection on an ultra low power multi-core architecture
inferredcites →https://doi.org/10.1109/dsd.2017.83openalex-snapshot
Loop Overhead Reduction Techniques for Coarse Grained Reconfigurable Architectures
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Prebypass: Software Register File Bypassing for Reduced Interconnection Architectures
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PathFinder: A Negotiation-Based Performance-Driven Router for FPGAs
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Blocks: Redesigning Coarse Grained Reconfigurable Architectures for Energy Efficiency
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2020 30th International Conference on Field-Programmable Logic and Applications (FPL)
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TTA-SIMD Soft Core Processors
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Efficient execution of augmented reality applications on mobile programmable accelerators
inferredcites →https://doi.org/10.1109/icassp40776.2020.9054613openalex-snapshot
Energy Efficient Acceleration Of Floating Point Applications Onto CGRA
inferredcites →https://doi.org/10.1109/icfpt56656.2022.9974339openalex-snapshot
Energy Efficient Design of Coarse-Grained Reconfigurable Architectures: Insights, Trends and Challenges
inferredcites →https://doi.org/10.1109/icfpt59805.2023openalex-snapshot
2023 International Conference on Field Programmable Technology (ICFPT)
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Transport-Triggered Soft Cores
inferredcites →https://doi.org/10.1109/isca45697.2020.00032openalex-snapshot
DSAGEN: Synthesizing Programmable Spatial Accelerators
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Snafu: An Ultra-Low-Power, Energy-Minimal CGRA-Generation Framework and Architecture
inferredcites →https://doi.org/10.1109/iscas.2017.8050238openalex-snapshot
A 142MOPS/mW integrated programmable array accelerator for smart visual processing
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Reliable and energy-efficient 1MHz 0.4V dynamically reconfigurable SoC for ExG applications in 40nm LP CMOS
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IEEE International Solid-State Circuits Conference (ISSCC 2008)
inferredcites →https://doi.org/10.1109/lca.2023.3268126openalex-snapshot
Canal: A Flexible Interconnect Generator for Coarse-Grained Reconfigurable Arrays
inferredcites →https://doi.org/10.1109/les.2018.2849267openalex-snapshot
i-DPs CGRA: An Interleaved-Datapaths Reconfigurable Accelerator for Embedded Bio-Signal Processing
inferredcites →https://doi.org/10.1109/lssc.2020.3012019openalex-snapshot
A 28-nm Coarse Grain 2D-Reconfigurable Array With Data Forwarding
inferredcites →https://doi.org/10.1109/micro.2012.17openalex-snapshot
Libra: Tailoring SIMD Execution Using Heterogeneous Hardware and Dynamic Configurability
inferredcites →https://doi.org/10.1109/micro.2016.7783755openalex-snapshot
Evaluating programmable architectures for imaging and vision applications
inferredcites →https://doi.org/10.1109/micro56248.2022.00046openalex-snapshot
RipTide: A Programmable, Energy-Minimal Dataflow Compiler and Architecture
inferredcites →https://doi.org/10.1109/samos.2016.7818353openalex-snapshot
Coarse grained reconfigurable architectures in the past 25 years: Overview and classification
inferredcites →https://doi.org/10.1109/samos35827.2015openalex-snapshot
2015 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS)
inferredcites →https://doi.org/10.1109/tbcas.2021.3120965openalex-snapshot
Multi-Level Optimization of an Ultra-Low Power BrainWave System for Non-Convulsive Seizure Detection
inferredcites →https://doi.org/10.1109/tc.2023.3257504openalex-snapshot
Acceleration of Control Intensive Applications on Coarse-Grained Reconfigurable Arrays for Embedded Systems
inferredcites →https://doi.org/10.1109/tcad.2018.2834397openalex-snapshot
An Energy-Efficient Integrated Programmable Array Accelerator and Compilation Flow for Near-Sensor Ultralow Power Processing
inferredcites →https://doi.org/10.1109/tcad.2021.3058313openalex-snapshot
ChordMap: Automated Mapping of Streaming Applications Onto CGRA
inferredcites →https://doi.org/10.1109/tcad.2021.3120541openalex-snapshot
Blocks: Challenging SIMDs and VLIWs With a Reconfigurable Architecture
inferredcites →https://doi.org/10.1109/tcad.2021.3132551openalex-snapshot
HiMap: Fast and Scalable High-Quality Mapping on CGRA via Hierarchical Abstraction
inferredcites →https://doi.org/10.1109/tcad.2022.3185544openalex-snapshot
A Reschedulable Dataflow-SIMD Execution for Increased Utilization in CGRA Cross-Domain Acceleration
inferredcites →https://doi.org/10.1109/tcsi.2017.2701499openalex-snapshot
HEAL-WEAR: An Ultra-Low Power Heterogeneous System for Bio-Signal Analysis
inferredcites →https://doi.org/10.1109/tmm.2006.880562openalex-snapshot
2007 IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP)
inferredcites →https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830509openalex-snapshot
Amber: A 367 GOPS, 538 GOPS/W 16nm SoC with a Coarse-Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra
inferredcites →https://doi.org/10.1145/1133981.1133997openalex-snapshot
Auto-vectorization of interleaved data for SIMD
inferredcites →https://doi.org/10.1145/1508128.1508158openalex-snapshot
SPR
inferredcites →https://doi.org/10.1145/2593069.2593198openalex-snapshot
Reduction Operator for Wide-SIMDs Reconsidered
inferredcites →https://doi.org/10.1145/2629610openalex-snapshot
ULP-SRP
inferredcites →https://doi.org/10.1145/2747875openalex-snapshot
Array Interleaving—An Energy-Efficient Data Layout Transformation
inferredcites →https://doi.org/10.1145/2845082openalex-snapshot
Integer Linear Programming-Based Scheduling for Transport Triggered Architectures
inferredcites →https://doi.org/10.1145/3061639.3062262openalex-snapshot
HyCUBE
inferredcites →https://doi.org/10.1145/3079856.3080255openalex-snapshot
Stream-Dataflow Acceleration
inferredcites →https://doi.org/10.1145/3079856.3080256openalex-snapshot
Plasticine
inferredcites →https://doi.org/10.1145/3323439.3323990openalex-snapshot
Towards Efficient Code Generation for Exposed Datapath Architectures
inferredcites →https://doi.org/10.1145/3352460.3358277openalex-snapshot
MANIC
inferredcites →https://doi.org/10.1145/3357375openalex-snapshot
A Survey of Coarse-Grained Reconfigurable Architecture and Design
inferredcites →https://doi.org/10.1145/3358177openalex-snapshot
CASCADE
inferredcites →https://doi.org/10.1145/3468874openalex-snapshot
CGRA-EAM—Rapid Energy and Area Estimation for Coarse-grained Reconfigurable Architectures
inferredcites →https://doi.org/10.1145/3489517.3530980openalex-snapshot
VWR2A
inferredcites →https://doi.org/10.1145/3503222.3507772openalex-snapshot
REVAMP: a systematic framework for heterogeneous CGRA realization
inferredcites →https://doi.org/10.1145/3508352.3549367openalex-snapshot
Spatz
inferredcites →https://doi.org/10.1145/3534933openalex-snapshot
AHA: An Agile Approach to the Design of Coarse-Grained Reconfigurable Accelerators and Compilers
inferredcites →https://doi.org/10.23919/date42667.2018openalex-snapshot
2018 Design, Automation & Test in Europe Conference & Exhibition (DATE)
inferredcites →https://doi.org/10.23919/date48585.2020.9116408openalex-snapshot
TRANSPIRE: An energy-efficient TRANSprecision floating-point Programmable archItectuRE

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

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Reconfigurable Domain‐Specific Architectures Based on Coarse‐Grained Operators in High‐Performance FPGAs
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Mage: a Decoupled Access-Execute CGRA tailored for Static Control Applications
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Flexible Hardware Accelerators for Ultra-Low Power Edge AI: The CONVOLVE Approach
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Cycle Count Estimation of VLIW Processors Using Machine Learning
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A 22nm Coarse-Grained Reconfigurable Array with Novel Features for Machine Learning and Digital Signal Processing
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DVHetero: A Framework for Designing and Validating Heterogeneous SoC with RISC-V Processor and CGRA
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CADAS: Communication-Aware Dynamic Scheduler on CGRAs for Large-Volume and Real-Time Processing
inferred← citeshttps://doi.org/10.23919/date69613.2026.11539365openalex-snapshot
Voltage Aware Approximate CGRA Synthesis for Energy Efficient DNN Inference
inferred← citeshttps://doi.org/10.23919/date69613.2026.11539616openalex-snapshot
Optimize edge AI processing through innovative compilation techniques
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