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Vector Extensions for Decision Support DBMS Acceleration
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1002/1520-684x(200007)31:8<79::aid-scj9>3.0.co;2-copenalex-snapshot
Acceleration of relational database operations on vector processors
inferredcites →https://doi.org/10.1007/978-3-642-32627-1_1openalex-snapshot
Shaping the Landscape of Industry Standard Benchmarks: Contributions of the Transaction Processing Performance Council (TPC)
inferredcites →https://doi.org/10.1016/0378-4754(88)90016-xopenalex-snapshot
Scientific computing on vector computers
inferredcites →https://doi.org/10.1016/j.micpro.2004.10.002openalex-snapshot
Multimedia extensions for general purpose microprocessors: a survey
inferredcites →https://doi.org/10.1109/40.865866openalex-snapshot
Implementing streaming SIMD extensions on the Pentium III processor
inferredcites →https://doi.org/10.1109/icde.2004.1319989openalex-snapshot
Improving hash join performance through prefetching
inferredcites →https://doi.org/10.1109/isca.2002.1003586openalex-snapshot
Tarantula: a vector extension to the alpha architecture
inferredcites →https://doi.org/10.1109/ispass.2007.363733openalex-snapshot
PTLsim: A Cycle Accurate Full System x86-64 Microarchitectural Simulator
inferredcites →https://doi.org/10.1109/l-ca.2011.4openalex-snapshot
DRAMSim2: A Cycle Accurate Memory System Simulator
inferredcites →https://doi.org/10.1109/micro.1997.645807openalex-snapshot
Out-of-order vector architectures
inferredcites →https://doi.org/10.1109/micro.1999.809445openalex-snapshot
Exploiting a new level of DLP in multimedia applications
inferredcites →https://doi.org/10.1109/micro.2002.1176257openalex-snapshot
Vector vs. superscalar and VLIW architectures for embedded multimedia benchmarks
inferredcites →https://doi.org/10.1109/mm.2006.41openalex-snapshot
Synergistic Processing in Cell's Multicore Architecture
inferredcites →https://doi.org/10.1109/sc.2006.62openalex-snapshot
The Potential Energy Efficiency of Vector Acceleration
inferredcites →https://doi.org/10.1145/1188455.1188537openalex-snapshot
Architecture---The potential energy efficiency of vector acceleration
inferredcites →https://doi.org/10.1145/1272743.1272747openalex-snapshot
Improving hash join performance through prefetching
inferredcites →https://doi.org/10.1145/1363189.1363195openalex-snapshot
Vectorized data processing on the cell broadband engine
inferredcites →https://doi.org/10.1145/1620585.1620588openalex-snapshot
Relational query coprocessing on graphics processors
inferredcites →https://doi.org/10.1145/165231.165266openalex-snapshot
An overview of Cray research computers including the Y-MP/C90 and the new MPP T3D
inferredcites →https://doi.org/10.1145/1995441.1995446openalex-snapshot
Vectorization vs. compilation in query execution
inferredcites →https://doi.org/10.1145/2000064.2000080openalex-snapshot
Exploring the tradeoffs between programmability and efficiency in data-parallel accelerators
inferredcites →https://doi.org/10.1145/264107.264201openalex-snapshot
Complexity-effective superscalar processors
inferredcites →https://doi.org/10.1145/279358.279363openalex-snapshot
Memory system characterization of commercial workloads
inferredcites →https://doi.org/10.1145/279361.279363openalex-snapshot
Memory system characterization of commercial workloads
inferredcites →https://doi.org/10.1145/305138.305148openalex-snapshot
Adding a vector unit to a superscalar processor
inferredcites →https://doi.org/10.1145/339647.339693openalex-snapshot
Vector instruction set support for conditional operations
inferredcites →https://doi.org/10.1145/564691.564709openalex-snapshot
Implementing database operations using SIMD instructions
inferredcites →https://doi.org/10.1145/564708.564709openalex-snapshot
Implementing database operations using SIMD instructions
inferredcites →https://doi.org/10.2200/s00193ed1v01y200905cac006openalex-snapshot
The Datacenter as a Computer: An Introduction to the Design of Warehouse-Scale Machines
inferredcites →https://doi.org/10.5555/266800.266816openalex-snapshot
Out-of-order vector architectures
inferredcites →https://doi.org/10.5555/320080.320093openalex-snapshot
Exploiting a new level of DLP in multimedia applications
inferredcites →https://doi.org/10.5555/774861.774892openalex-snapshot
Vector vs. superscalar and VLIW architectures for embedded multimedia benchmarks
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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Accelerating Hash-Based Query Processing Operations on FPGAs by a Hash Table Caching Technique
inferred← citeshttps://doi.org/10.1016/j.micpro.2017.04.018openalex-snapshot
AxleDB: A novel programmable query processing platform on FPGA
inferred← citeshttps://doi.org/10.1109/access.2019.2917698openalex-snapshot
A Survey of Computer Architecture Simulation Techniques and Tools
inferred← citeshttps://doi.org/10.1109/fccm.2015.28openalex-snapshot
HATCH: Hash Table Caching in Hardware for Efficient Relational Join on FPGA
inferred← citeshttps://doi.org/10.1109/hpca.2015.7056019openalex-snapshot
VSR sort: A novel vectorised sorting algorithm & architecture extensions for future microprocessors
inferred← citeshttps://doi.org/10.1109/hpca56546.2023.10070958openalex-snapshot
VAQUERO: A Scratchpad-based Vector Accelerator for Query Processing
inferred← citeshttps://doi.org/10.1109/iccd.2016.7753351openalex-snapshot
×86 computer architecture simulators: A comparative study
inferred← citeshttps://doi.org/10.1109/icfpt56656.2022.9974596openalex-snapshot
Automated Generation and Orchestration of Stream Processing Pipelines on FPGAs
inferred← citeshttps://doi.org/10.1109/isca.2016.44openalex-snapshot
Future Vector Microprocessor Extensions for Data Aggregations
inferred← citeshttps://doi.org/10.1117/12.2628136openalex-snapshot
High-efficiency vector and scalar fused load store unit design
inferred← citeshttps://doi.org/10.1145/2588555.2593677openalex-snapshot
An application-specific instruction set for accelerating set-oriented database primitives
inferred← citeshttps://doi.org/10.1145/2903150.2903485openalex-snapshot
Towards low-power embedded vector processor
inferred← citeshttps://doi.org/10.1145/3007787.3001182openalex-snapshot
Future vector microprocessor extensions for data aggregations
inferred← citeshttps://doi.org/10.1145/3055167.3055174openalex-snapshot
Energy-efficient Database Machines
inferred← citeshttps://doi.org/10.1145/3075618openalex-snapshot
An Integrated Vector-Scalar Design on an In-Order ARM Core
inferred← citeshttps://doi.org/10.1145/3352460.3358272openalex-snapshot
Leveraging Caches to Accelerate Hash Tables and Memoization
inferred← citeshttps://doi.org/10.1186/s12859-022-04799-4openalex-snapshot
Optimize data-driven multi-agent simulation for COVID-19 transmission
inferred← citeshttps://doi.org/10.13140/rg.2.2.13364.76169openalex-snapshot
A Comparison of x86 Computer Architecture Simulators
inferred← citeshttps://doi.org/10.14445/22312803/ijctt-v56p102openalex-snapshot
Accelerating Hash Join Performance by Exploiting Data Distribution
inferred← citeshttps://doi.org/10.21203/rs.3.rs-1378622/v1openalex-snapshot
Optimize Data-Driven Multi-Agent Simulation for COVID-19 Transmission
inferred← citeshttps://doi.org/10.2200/s00650ed1v01y201505cac033openalex-snapshot
Customizable Computing
inferred← citeshttps://doi.org/10.5821/dissertation-2117-107712openalex-snapshot
Design of energy-efficient vector units for in-order cores
inferred← citeshttps://doi.org/10.5821/dissertation-2117-129265openalex-snapshot
Advanced analytics through FPGA based query processing and deep reinforcement learning
inferred← citeshttps://doi.org/10.5821/dissertation-2117-96236openalex-snapshot
Specialization and reconfiguration of lightweight mobile processors for data-parallel applications
inferred← citeshttps://doi.org/10.5821/dissertation-2117-98086openalex-snapshot
Novel vector architectures for data management
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