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The Potential Energy Efficiency of Vector Acceleration

https://doi.org/10.1109/sc.2006.62
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1109/hpca.1996.501193openalex-snapshot
Decoupled vector architectures
inferredcites →https://doi.org/10.1109/hpca.1997.569677openalex-snapshot
Multithreaded vector architectures
inferredcites →https://doi.org/10.1109/isca.2002.1003586openalex-snapshot
Tarantula: a vector extension to the alpha architecture
inferredcites →https://doi.org/10.1109/isscc.1997.585323openalex-snapshot
A 600 MHz superscalar RISC microprocessor with out-of-order execution
inferredcites →https://doi.org/10.1109/micro.2002.1176257openalex-snapshot
Vector vs. superscalar and VLIW architectures for embedded multimedia benchmarks
inferredcites →https://doi.org/10.1109/micro.2002.1176258openalex-snapshot
Orion: a power-performance simulator for interconnection networks
inferredcites →https://doi.org/10.1109/micro.2004.9openalex-snapshot
Cache Refill/Access Decoupling for Vector Machines
inferredcites →https://doi.org/10.1109/mm.2004.90openalex-snapshot
The vector-thread architecture
inferredcites →https://doi.org/10.1145/1048935.1050187openalex-snapshot
Merrimac
inferredcites →https://doi.org/10.1145/1465482.1465560openalex-snapshot
Validity of the single processor approach to achieving large scale computing capabilities
inferredcites →https://doi.org/10.1145/305138.305148openalex-snapshot
Adding a vector unit to a superscalar processor
inferredcites →https://doi.org/10.1145/342001.339657openalex-snapshot
Wattch
inferredcites →https://doi.org/10.1145/859618.859664openalex-snapshot
Overcoming the limitations of conventional vector processors

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/s11227-019-02841-6openalex-snapshot
Efficiency analysis of modern vector architectures: vector ALU sizes, core counts and clock frequencies
inferred← citeshttps://doi.org/10.1016/b978-0-12-396958-3.00012-3openalex-snapshot
CMOS Photonics for High Performance Interconnects
inferred← citeshttps://doi.org/10.1016/j.cpc.2008.01.045openalex-snapshot
On ERI sorting for SIMD execution of large-scale Hartree–Fock SCF
inferred← citeshttps://doi.org/10.1109/ipdps54959.2023.00024openalex-snapshot
Accelerating CNN inference on long vector architectures via co-design
inferred← citeshttps://doi.org/10.1109/isqed.2013.6523602openalex-snapshot
On the selection of adder unit in energy efficient vector processing
inferred← citeshttps://doi.org/10.1109/isvlsi.2015.23openalex-snapshot
Joint Circuit-System Design Space Exploration of Multiplier Unit Structure for Energy-Efficient Vector Processors
inferred← citeshttps://doi.org/10.1109/micro.2012.24openalex-snapshot
Vector Extensions for Decision Support DBMS Acceleration
inferred← citeshttps://doi.org/10.1109/micro56248.2022.00025openalex-snapshot
big.VLITTLE: On-Demand Data-Parallel Acceleration for Mobile Systems on Chip
inferred← citeshttps://doi.org/10.1109/sbac-pad.2012.35openalex-snapshot
On the Efficiency of Register File versus Broadcast Interconnect for Collective Communications in Data-Parallel Hardware Accelerators
inferred← citeshttps://doi.org/10.1109/sbac-pad.2014.13openalex-snapshot
ASIC Design of Shared Vector Accelerators for Multicore Processors
inferred← citeshttps://doi.org/10.5821/dissertation-2117-106493openalex-snapshot
On the design of power- and energy-efficient functional units for vector processors
inferred← citeshttps://doi.org/10.5821/dissertation-2117-107712openalex-snapshot
Design of energy-efficient vector units for in-order cores
inferred← citeshttps://doi.org/10.5821/dissertation-2117-98086openalex-snapshot
Novel vector architectures for data management
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