On the public citation graph

Accurate Fine-Grained Processor Power Proxies

0 signed · 62 inferred · view as graph

Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.

Is this your work? Sign in with ORCID and put your name on the claims that are yours.
Claim with ORCID
Reference health. See whether every reference in this work resolves to a known work and none has been retracted — and get a dated CiteStamped badge you can embed.
See reference health

What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/s10586-007-0045-4openalex-snapshot
Power capping: a prelude to power shifting
inferredcites →https://doi.org/10.1109/greencomp.2010.5598313openalex-snapshot
Portable, scalable, per-core power estimation for intelligent resource management
inferredcites →https://doi.org/10.1109/hpca.2009.4798264openalex-snapshot
CAMP: A technique to estimate per-structure power at run-time using a few simple parameters
inferredcites →https://doi.org/10.1109/hpca.2010.5416627openalex-snapshot
Architecting for power management: The IBM® POWER7™ approach
inferredcites →https://doi.org/10.1109/hpca.2011.5749746openalex-snapshot
Abstraction and microarchitecture scaling in early-stage power modeling
inferredcites →https://doi.org/10.1109/isscc.2008.4523072openalex-snapshot
A 65nm 2-Billion-Transistor Quad-Core Itanium® Processor
inferredcites →https://doi.org/10.1109/isscc.2010.5434076openalex-snapshot
An x86-64 core implemented in 32nm SOI CMOS
inferredcites →https://doi.org/10.1109/jssc.2008.2007150openalex-snapshot
A 65 nm 2-Billion Transistor Quad-Core Itanium Processor
inferredcites →https://doi.org/10.1109/mm.2011.29openalex-snapshot
Introducing the Adaptive Energy Management Features of the Power7 Chip
inferredcites →https://doi.org/10.1145/1077603.1077657openalex-snapshot
Power prediction for intel XScale® processors using performance monitoring unit events
inferredcites →https://doi.org/10.1145/1807128.1807136openalex-snapshot
Virtual machine power metering and provisioning
inferredcites →https://doi.org/10.1145/2155620.2155622openalex-snapshot
Active management of timing guardband to save energy in POWER7
inferredcites →https://doi.org/10.1145/566726.566736openalex-snapshot
The benefits of event
inferredcites →https://doi.org/10.1147/jrd.2011.2114250openalex-snapshot
Adaptive energy-management features of the IBM POWER7 chip
inferredcites →https://doi.org/10.5445/ir/1000027240openalex-snapshot
Energy Management for Hypervisor-Based Virtual Machines

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/978-3-030-60939-9_13openalex-snapshot
Fine-Grained Power Modeling of Multicore Processors Using FFNNs
inferred← citeshttps://doi.org/10.1007/s10766-022-00730-9openalex-snapshot
Fine-Grained Power Modeling of Multicore Processors Using FFNNs
inferred← citeshttps://doi.org/10.1109/ccgrid49817.2020.00-54openalex-snapshot
Cross Architectural Power Modelling
inferred← citeshttps://doi.org/10.1109/e2sc.2014.12openalex-snapshot
Instrumentation for Accurate Energy-to-Solution Measurements of a Texas Instruments TMS320C6678 Digital Signal Processor and Its DDR3 Memory
inferred← citeshttps://doi.org/10.1109/e2sc.2016.016openalex-snapshot
Neural Network-Based Task Scheduling with Preemptive Fan Control
inferred← citeshttps://doi.org/10.1109/epeps.2017.8329719openalex-snapshot
Maximum power specification management feature in Intel Xeon CPUs
inferred← citeshttps://doi.org/10.1109/hipc.2017.00020openalex-snapshot
Support for Power Efficient Proactive Cooling Mechanisms
inferred← citeshttps://doi.org/10.1109/hpca.2018.00070openalex-snapshot
Power and Energy Characterization of an Open Source 25-Core Manycore Processor
inferred← citeshttps://doi.org/10.1109/icdcs.2017.235openalex-snapshot
Virtual Machine Power Accounting with Shapley Value
inferred← citeshttps://doi.org/10.1109/icdcs.2018.00038openalex-snapshot
Non-IT Energy Accounting in Virtualized Datacenter
inferred← citeshttps://doi.org/10.1109/icecs.2013.6815570openalex-snapshot
Ultra compact, quadratic power proxies for multi-core processors
inferred← citeshttps://doi.org/10.1109/icpp.2013.101openalex-snapshot
Relating Application Memory Activity to Processor Power
inferred← citeshttps://doi.org/10.1109/iiswc.2016.7581266openalex-snapshot
Characterization and mitigation of power contention across multiprogrammed workloads
inferred← citeshttps://doi.org/10.1109/isca52012.2021.00012openalex-snapshot
Energy Efficiency Boost in the AI-Infused POWER10 Processor
inferred← citeshttps://doi.org/10.1109/isca59077.2024.00063openalex-snapshot
BlitzCoin: Fully Decentralized Hardware Power Management for Accelerator-Rich SoCs
inferred← citeshttps://doi.org/10.1109/islped.2015.7273513openalex-snapshot
FreqLeak: A frequency step based method for efficient leakage power characterization in a system
inferred← citeshttps://doi.org/10.1109/micro.2014.17openalex-snapshot
PPEP: Online Performance, Power, and Energy Prediction Framework and DVFS Space Exploration
inferred← citeshttps://doi.org/10.1109/micro.2016.7783758openalex-snapshot
Ti-states: Processor power management in the temperature inversion region
inferred← citeshttps://doi.org/10.1109/micro50266.2020.00088openalex-snapshot
FlexWatts: A Power- and Workload-Aware Hybrid Power Delivery Network for Energy-Efficient Microprocessors
inferred← citeshttps://doi.org/10.1109/pdp.2014.112openalex-snapshot
Modeling CPU Energy Consumption of HPC Applications on the IBM POWER7
inferred← citeshttps://doi.org/10.1109/tcad.2017.2661808openalex-snapshot
Kalman Predictor-Based Proactive Dynamic Thermal Management for 3-D NoC Systems With Noisy Thermal Sensors
inferred← citeshttps://doi.org/10.1109/tcad.2018.2873210openalex-snapshot
OPTiC: Optimizing Collaborative CPU–GPU Computing on Mobile Devices With Thermal Constraints
inferred← citeshttps://doi.org/10.1109/tcad.2020.3013062openalex-snapshot
A Lightweight Nonlinear Methodology to Accurately Model Multicore Processor Power
inferred← citeshttps://doi.org/10.1109/vlsid.2015.84openalex-snapshot
FirmLeak: A Framework for Efficient and Accurate Runtime Estimation of Leakage Power by Firmware
inferred← citeshttps://doi.org/10.1145/2451116.2451124openalex-snapshot
Power containers
inferred← citeshttps://doi.org/10.1145/2490301.2451124openalex-snapshot
Power containers
inferred← citeshttps://doi.org/10.1145/2499368.2451124openalex-snapshot
Power containers
inferred← citeshttps://doi.org/10.1145/2540708.2540727openalex-snapshot
Crank it up or dial it down
inferred← citeshttps://doi.org/10.1145/2541228.2555291openalex-snapshot
Hardware support for accurate per-task energy metering in multicore systems
inferred← citeshttps://doi.org/10.1145/2658988openalex-snapshot
Hybrid Cache Designs for Reliable Hybrid High and Ultra-Low Voltage Operation
inferred← citeshttps://doi.org/10.1145/2742854.2742880openalex-snapshot
Just-in-time component-wise power and thermal modeling
inferred← citeshttps://doi.org/10.1145/2830772.2830797openalex-snapshot
Rubik
inferred← citeshttps://doi.org/10.1145/2830772.2830824openalex-snapshot
Adaptive guardband scheduling to improve system-level efficiency of the POWER7+
inferred← citeshttps://doi.org/10.1145/3466752.3480064openalex-snapshot
APOLLO: An Automated Power Modeling Framework for Runtime Power Introspection in High-Volume Commercial Microprocessors
inferred← citeshttps://doi.org/10.1145/3508352.3549427openalex-snapshot
DEEP
inferred← citeshttps://doi.org/10.1145/3569052.3578927openalex-snapshot
Efficient Runtime Power Modeling with On-Chip Power Meters
inferred← citeshttps://doi.org/10.1147/jrd.2015.2446872openalex-snapshot
Robust power management in the IBM z13
inferred← citeshttps://doi.org/10.1147/jrd.2020.3008143openalex-snapshot
Proactive power management in IBM z15
inferred← citeshttps://doi.org/10.1371/journal.pone.0188428openalex-snapshot
Evaluating architecture impact on system energy efficiency
inferred← citeshttps://doi.org/10.14529/jsfi180403openalex-snapshot
A Study on Cross-Architectural Modelling of Power Consumption Using Neural Networks
inferred← citeshttps://doi.org/10.14989/doctor.k17992openalex-snapshot
Modeling, Characterization and Compensation of Performance Variability using On-chip Monitor Circuits for Energy-efficient LSI
inferred← citeshttps://doi.org/10.17760/d20292369openalex-snapshot
Dynamic voltage and frequency scaling for 3D graphics applications on the state-of-the-art mobile GPUs
inferred← citeshttps://doi.org/10.3233/978-1-61499-843-3-804openalex-snapshot
Power Modelling for Heterogeneous Cloud-Edge Data Centers
inferred← citeshttps://doi.org/10.5555/2616606.2617081openalex-snapshot
Unified, ultra compact, quadratic power proxies for multi-core processors
inferred← citeshttps://doi.org/10.5821/dissertation-2117-96355openalex-snapshot
Per-task energy metering and accounting in the multicore era
inferred← citeshttps://doi.org/10.70675/02a57407z3126z44afz8b2fz0b34579b21f0openalex-snapshot
Energy efficiency optimization in 28 nm FD-SOI : circuit design for adaptive clocking and power-temperature aware digital SoCs
inferred← citeshttps://doi.org/10.7282/t3zk5dz2openalex-snapshot
Active low-power modes for main memory
Editorial review for independent work. ICSAC — the Institute for Complexity Science and Advanced Computing — runs a structured editorial panel for researchers publishing outside journals, and publishes on CiteStamp rails. Submission is free and goes through ORCID: icsacinstitute.org/submit.