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A Front-End Execution Architecture for High Energy Efficiency

https://doi.org/10.1109/micro.2014.35
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1109/40.491460openalex-snapshot
The Mips R10000 superscalar microprocessor
inferredcites →https://doi.org/10.1109/40.755465openalex-snapshot
The Alpha 21264 microprocessor
inferredcites →https://doi.org/10.1109/isca.1998.694770openalex-snapshot
Memory dependence prediction using store sets
inferredcites →https://doi.org/10.1109/isca.2001.937452openalex-snapshot
Energy-effective issue logic
inferredcites →https://doi.org/10.1109/isca.2005.43openalex-snapshot
RENO: a rename-based instruction optimizer
inferredcites →https://doi.org/10.1109/isscc.2006.1696230openalex-snapshot
A 240ps 64b carry-lookahead adder in 90nm CMOS
inferredcites →https://doi.org/10.1109/jssc.2006.881557openalex-snapshot
A 6.2-GFlops Floating-Point Multiply-Accumulator With Conditional Normalization
inferredcites →https://doi.org/10.1109/jssc.2006.885055openalex-snapshot
A 9-GHz 65-nm Intel® Pentium 4 Processor Integer Execution Unit
inferredcites →https://doi.org/10.1109/micro.2010.43openalex-snapshot
Register Cache System Not for Latency Reduction Purpose
inferredcites →https://doi.org/10.1109/vlsit.2012.6242496openalex-snapshot
A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors
inferredcites →https://doi.org/10.1145/1080695.1069980openalex-snapshot
RENO
inferredcites →https://doi.org/10.1145/1669112.1669172openalex-snapshot
McPAT
inferredcites →https://doi.org/10.1145/1815961.1815966openalex-snapshot
Forwardflow
inferredcites →https://doi.org/10.1145/279358.279378openalex-snapshot
Memory dependence prediction using store sets
inferredcites →https://doi.org/10.1145/339647.339708openalex-snapshot
Multiple-banked register file architectures
inferredcites →https://doi.org/10.1145/342001.339708openalex-snapshot
Multiple-banked register file architectures
inferredcites →https://doi.org/10.1145/379240.379266openalex-snapshot
Energy-effective issue logic
inferredcites →https://doi.org/10.1145/859618.859623openalex-snapshot
Half-price architecture
inferredcites →https://doi.org/10.1145/859622.859623openalex-snapshot
Half-price architecture
inferredcites →https://doi.org/10.1147/jrd.2011.2127330openalex-snapshot
IBM POWER7 multicore server processor

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/978-3-319-77610-1_16openalex-snapshot
A Tightly Coupled Heterogeneous Core with Highly Efficient Low-Power Mode
inferred← citeshttps://doi.org/10.1109/hpca47549.2020.00039openalex-snapshot
CASINO Core Microarchitecture: Generating Out-of-Order Schedules Using Cascaded In-Order Scheduling Windows
inferred← citeshttps://doi.org/10.1109/hpca47549.2020.00042openalex-snapshot
Delay and Bypass: Ready and Criticality Aware Instruction Scheduling in Out-of-Order Processors
inferred← citeshttps://doi.org/10.1109/iccd46524.2019.00103openalex-snapshot
Freeflow Core: Enhancing Performance of In-Order Cores with Energy Efficiency
inferred← citeshttps://doi.org/10.1109/iolts59296.2023.10224863openalex-snapshot
ERrOR: Improving Performance and Fault Tolerance Using Early Execution
inferred← citeshttps://doi.org/10.1109/isca.2016.45openalex-snapshot
Efficiently Scaling Out-of-Order Cores for Simultaneous Multithreading
inferred← citeshttps://doi.org/10.1109/isca66397.2026.00050openalex-snapshot
Hierarchical Wakeup Logic of the Issue Queue for High Scalability
inferred← citeshttps://doi.org/10.1109/micro.2018.00019openalex-snapshot
STRAIGHT: Hazardless Processor Architecture Without Register Renaming
inferred← citeshttps://doi.org/10.1109/micro61859.2024.00044openalex-snapshot
Localizing the Tag Comparisons in the Wakeup Logic to Reduce Energy Consumption of the Issue Queue
inferred← citeshttps://doi.org/10.1109/micro61859.2024.00101openalex-snapshot
Scalar Vector Runahead
inferred← citeshttps://doi.org/10.1109/tc.2017.2770126openalex-snapshot
Simultaneous and Speculative Thread Migration for Improving Energy Efficiency of Heterogeneous Core Architectures
inferred← citeshttps://doi.org/10.1109/ubmk.2019.8907005openalex-snapshot
iMODE (interactive MOod Detection Engine) Processor
inferred← citeshttps://doi.org/10.1109/vlsid60093.2024.00067openalex-snapshot
Early Execution for Soft Error Detection
inferred← citeshttps://doi.org/10.1145/3007787.3001183openalex-snapshot
Efficiently scaling out-of-order cores for simultaneous multithreading
inferred← citeshttps://doi.org/10.1145/3079856.3080219openalex-snapshot
XPro
inferred← citeshttps://doi.org/10.1145/3140659.3080219openalex-snapshot
XPro
inferred← citeshttps://doi.org/10.1145/3170433openalex-snapshot
A Case for a More Effective, Power-Efficient Turbo Boosting
inferred← citeshttps://doi.org/10.1145/3368474.3368496openalex-snapshot
Energy Efficient Runahead Execution on a Tightly Coupled Heterogeneous Core
inferred← citeshttps://doi.org/10.1145/3410463.3414629openalex-snapshot
The Forward Slice Core Microarchitecture
inferred← citeshttps://doi.org/10.1145/3499424openalex-snapshot
The Forward Slice Core: A High-Performance, Yet Low-Complexity Microarchitecture
inferred← citeshttps://doi.org/10.1145/3503222.3507745openalex-snapshot
CRISP: critical slice prefetching
inferred← citeshttps://doi.org/10.1145/3506704openalex-snapshot
Dependence-aware Slice Execution to Boost MLP in Slice-out-of-order Cores
inferred← citeshttps://doi.org/10.1145/3613424.3614272openalex-snapshot
Clockhands: Rename-free Instruction Set Architecture for Out-of-order Processors
inferred← citeshttps://doi.org/10.1145/3665314.3670805openalex-snapshot
ReOVE: Restricted Out-of-Order Execution for Superscalar Processors with Vector Extension
inferred← citeshttps://doi.org/10.1145/3676536.3676757openalex-snapshot
Sustainable High-Performance Instruction Selection for Superscalar Processors
inferred← citeshttps://doi.org/10.1587/transinf.2015edp7270openalex-snapshot
Improvement of Renamed Trace Cache through the Reduction of Dependent Path Length for High Energy Efficiency
inferred← citeshttps://doi.org/10.1587/transinf.2015edp7316openalex-snapshot
FXA: Executing Instructions in Front-End for Energy Efficiency
inferred← citeshttps://doi.org/10.1587/transinf.2016pap0030openalex-snapshot
An Inductive Method to Select Simulation Points
inferred← citeshttps://doi.org/10.23919/date.2019.8715034openalex-snapshot
FIFOrder MicroArchitecture: Ready-Aware Instruction Scheduling for OoO Processors
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