On the public citation graph
Register Cache System Not for Latency Reduction Purpose
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1016/0026-2692(93)90111-qopenalex-snapshot
Computer architecture: a quantitative approach
inferredcites →https://doi.org/10.1109/hpca.2000.824366openalex-snapshot
Register organization for media processing
inferredcites →https://doi.org/10.1109/iccd.1995.528826openalex-snapshot
Caching processor general registers
inferredcites →https://doi.org/10.1109/icpp.2006.20openalex-snapshot
Address-Value Decoupling for Early Register Deallocation
inferredcites →https://doi.org/10.1109/isca.2002.1003559openalex-snapshot
Increasing processor performance by implementing deeper pipelines
inferredcites →https://doi.org/10.1109/isca.2004.1310783openalex-snapshot
Use-based register caching with decoupled indexing
inferredcites →https://doi.org/10.1109/isscc.2002.992247openalex-snapshot
Design of an 8-wide superscalar RISC microprocessor with simultaneous multithreading
inferredcites →https://doi.org/10.1109/isscc.2002.993068openalex-snapshot
Design of an 8-wide superscalar RISC microprocessor with simultaneous multithreading
inferredcites →https://doi.org/10.1109/isscc.2006.1696066openalex-snapshot
A 9GHz 65nm Intel Pentium 4 Processor Integer Execution Core
inferredcites →https://doi.org/10.1109/micro.1995.476811openalex-snapshot
The performance impact of incomplete bypassing in processor pipelines
inferredcites →https://doi.org/10.1109/micro.2002.1176235openalex-snapshot
Characterizing and predicting value degree of use
inferredcites →https://doi.org/10.1145/1028176.1006724openalex-snapshot
Use-Based Register Caching with Decoupled Indexing
inferredcites →https://doi.org/10.1145/268806.268810openalex-snapshot
The SimpleScalar tool set, version 2.0
inferredcites →https://doi.org/10.1145/339647.339708openalex-snapshot
Multiple-banked register file architectures
inferredcites →https://doi.org/10.1145/342001.339708openalex-snapshot
Multiple-banked register file architectures
inferredcites →https://doi.org/10.1145/545214.545219openalex-snapshot
Increasing processor performance by implementing deeper pipelines
inferredcites →https://doi.org/10.5555/225160.225170openalex-snapshot
The performance impact of incomplete bypassing in processor pipelines
inferredcites →https://doi.org/10.5555/320080.320108openalex-snapshot
Delaying physical register allocation through virtual-physical registers
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1002/cpe.3906openalex-snapshot
A survey of techniques for designing and managing CPU register file
inferred← citeshttps://doi.org/10.1007/s10617-022-09264-2openalex-snapshot
Selective register-file cache: an energy saving technique for embedded processor architecture
inferred← citeshttps://doi.org/10.1109/candar.2015.106openalex-snapshot
An Inductive Method to Select Simulation Points
inferred← citeshttps://doi.org/10.1109/candar.2015.85openalex-snapshot
Register Port Prediction for a Banked Register File
inferred← citeshttps://doi.org/10.1109/iccd53106.2021.00070openalex-snapshot
Compiling and Optimizing Real-world Programs for STRAIGHT ISA
inferred← citeshttps://doi.org/10.1109/iccd65941.2025.00103openalex-snapshot
Register Bridging: A Lightweight Microarchitectural Approach for Skipping Overhead Instructions in Distance-Based ISA Processors
inferred← citeshttps://doi.org/10.1109/icnc.2012.66openalex-snapshot
STRAIGHT: Realizing a Lightweight Large Instruction Window by Using Eventually Consistent Distributed Registers
inferred← citeshttps://doi.org/10.1109/isca59077.2024.00075openalex-snapshot
Memento: An Adaptive, Compiler-Assisted Register File Cache for GPUs
inferred← citeshttps://doi.org/10.1109/micro.2014.35openalex-snapshot
A Front-End Execution Architecture for High Energy Efficiency
inferred← citeshttps://doi.org/10.1109/socc.2011.6085113openalex-snapshot
Low power tri-state register files design for modern out-of-order processors
inferred← citeshttps://doi.org/10.1109/southeastcon44009.2020.9368300openalex-snapshot
Execution Array Memory Array Processor (XarMa)
inferred← citeshttps://doi.org/10.1109/tc.2015.2395436openalex-snapshot
Block-Precise Processors: Low-Power Processors with Reduced Operand Store Accesses and Result Broadcasts
inferred← citeshttps://doi.org/10.1109/tvlsi.2014.2334136openalex-snapshot
TM-RF: Aging-Aware Power-Efficient Register File Design for Modern Microprocessors
inferred← citeshttps://doi.org/10.1145/2000064.2000093openalex-snapshot
Energy-efficient mechanisms for managing thread context in throughput processors
inferred← citeshttps://doi.org/10.1145/2024723.2000093openalex-snapshot
Energy-efficient mechanisms for managing thread context in throughput processors
inferred← citeshttps://doi.org/10.1145/2166879.2166882openalex-snapshot
A Hierarchical Thread Scheduler and Register File for Energy-Efficient Throughput Processors
inferred← citeshttps://doi.org/10.1145/3419973openalex-snapshot
Highly Concurrent Latency-tolerant Register Files for GPUs
inferred← citeshttps://doi.org/10.1145/3544838openalex-snapshot
HAIR: Halving the Area of the Integer Register File with Odd/Even Banking
inferred← citeshttps://doi.org/10.1145/3578360.3580263openalex-snapshot
A Sound and Complete Algorithm for Code Generation in Distance-Based ISA
inferred← citeshttps://doi.org/10.1145/3613424.3614272openalex-snapshot
Clockhands: Rename-free Instruction Set Architecture for Out-of-order Processors
inferred← citeshttps://doi.org/10.1587/transele.e100.c.232openalex-snapshot
Design of a Register Cache System with an Open Source Process Design Kit for 45nm Technology
inferred← citeshttps://doi.org/10.1587/transele.e100.c.245openalex-snapshot
Applying Razor Flip-Flops to SRAM Read Circuits
inferred← citeshttps://doi.org/10.1587/transinf.2015edp7270openalex-snapshot
Improvement of Renamed Trace Cache through the Reduction of Dependent Path Length for High Energy Efficiency
inferred← citeshttps://doi.org/10.1587/transinf.2015edp7316openalex-snapshot
FXA: Executing Instructions in Front-End for Energy Efficiency
inferred← citeshttps://doi.org/10.1587/transinf.2016edp7414openalex-snapshot
Skewed Multistaged Multibanked Register File for Area and Energy Efficiency
inferred← citeshttps://doi.org/10.1587/transinf.2016pap0030openalex-snapshot
An Inductive Method to Select Simulation Points
inferred← citeshttps://doi.org/10.2197/ipsjjip.26.696openalex-snapshot
Bank-Aware Instruction Scheduler for a Multibanked Register File
inferred← citeshttps://doi.org/10.3384/diss.diva-130723openalex-snapshot
Design of Energy-Efficient High-Performance ASIP-DSP Platforms
inferred← citeshttps://doi.org/10.48550/arxiv.2010.09330openalex-snapshot
Enabling High-Capacity, Latency-Tolerant, and Highly-Concurrent GPU Register Files via Software/Hardware Cooperation
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