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The AMD opteron processor for multiprocessor servers

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inferredcites →https://doi.org/10.1017/9789464562736.014openalex-snapshot
Technical Description
inferredcites →https://doi.org/10.1109/12.381947openalex-snapshot
Effective hardware-based data prefetching for high-performance processors
inferredcites →https://doi.org/10.1109/40.877950openalex-snapshot
The AzusA 16-way itanium server

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

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On Complexity of Collective Communications on a Fat Cube Topology
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Pipelining to Reduce the Power
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General-Purpose Multi-core Processors
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SOI Circuits
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Interconnect Modeling for Homogeneous and Heterogeneous Multiprocessors
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Case Studies on the Impact and Challenges of Heterogeneous NUMA Architectures for HPC
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Performance Evaluation of Evolutionary Multi-core and Aggressively Multi-threaded Processor Architectures
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Decoupled State-Execute Architecture
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A HyperTransport 3 Physical Layer Interface for FPGAs
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Session-Based Compilation Framework for Multicore Programming
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Exploring the Architecture of a Stream Register-Based Snoop Filter
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Reducing Energy Usage with Memory and Computation-Aware Dynamic Frequency Scaling
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A Cluster Computer Performance Predictor for Memory Scheduling
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Rechnerarchitekturen für Parallele und Verteilte Systeme
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A new degree of freedom for memory allocation in clusters
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B-Queue: Efficient and Practical Queuing for Fast Core-to-Core Communication
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DEAM: Decoupled, Expressive, Area-Efficient Metadata Cache
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Optical interconnection networks in advanced computing systems
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SMTp
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Power-aware operand delivery
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Predictor virtualization
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Predictor virtualization
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Sams
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Phantom-BTB
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Phantom-BTB
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Memory mapped ECC
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Memory mapped ECC
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Flexible cache error protection using an ECC FIFO
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CoRAM
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The gem5 simulator
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VSim
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Improving System Energy Efficiency with Memory Rank Subsetting
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Improving coherence protocol reactiveness by trading bandwidth for latency
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Viper
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XPoint cache
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LIGERO
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Phantom-BTB
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Implicit-storing and redundant-encoding-of-attribute information in error-correction-codes
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The benefit of SMT in the multi-core era
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The benefit of SMT in the multi-core era
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The benefit of SMT in the multi-core era
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Scratchpad-Memory Management for Multi-Threaded Applications on Many-Core Architectures
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Analytical Performance Models for NoCs with Multiple Priority Traffic Classes
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Towards practical multikernel OSes with MySyS
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Loupe: Driving the Development of OS Compatibility Layers
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Token coherence
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SIP server performance on multicore systems
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The reverse-acceleration model for programming petascale hybrid systems
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Decomposing the load-store queue by function for power reduction and scalability
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Virtual Prototyping and Performance Analysis of Two Memory Architectures
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Detecting Resource Contention in Virtualized Systems
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A Subscriber-Oriented Interference Detection and Mitigation System for Cloud-Based Web Services
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Analysis of Inter-Chip Communication Patterns on Multi-Core Distributed Shared-Memory Computers
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Processor Abstraction in Computer System Models
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高性能多核处理器申威1600
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Fast secure virtualization for the ARM platform
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PCubeS Type Architecture and IT Programming Language
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The Partitioned Parallel Processing Spaces (PCubeS) Type Architecture
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Victim Migration: Dynamically Adapting Between Private and Shared CMP Caches
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Summary of multi-core hardware and programming model investigations
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Retrospective Study of Performance and Power Consumption of Computer Systems
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Processor Microarchitecture: An Implementation Perspective
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Topology-aware virtual resource management for heterogeneous multicore systems
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A Regression Approach to Execution Time Estimation for Programs Running on Multicore Systems
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Application aware performance, power consumption, and reliability tradeoff
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High-Bandwidth Memory Accessing Pipeline of General Purpose Processor
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Steganography -- coding and intercepting the information from encoded pictures in the absence of any initial information
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Optimization of Discrete-parameter Multiprocessor Systems using a Novel Ergodic Interpolation Technique
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Scheduling Local and Remote Memory in Cluster Computers
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Efficient techniques to provide scalability for token-based cache coherence protocols.
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Hardware support for control transfers in code caches
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Using dynamic binary translation to fuse dependent instructions
inferred← citeshttps://doi.org/10.58088/d1dc-c577openalex-snapshot
Tapestry: weaving execution and synchronization models
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Soft error mitigation techniques for future chip multiprocessors
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Microprocessor architecture: from simple pipelines to chip multiprocessors
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Mouvement de données et placement des tâches pour les communications haute performance sur machines hiérarchiques
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De l’exécution structurée d’applications scientifiques OpenMP sur architectures hiérarchiques
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A Computational Approach to Custom Data Representation for Hardware Accelerators
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