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The gem5 simulator

https://doi.org/10.1145/2024716.2024718

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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/978-1-4419-6175-4openalex-snapshot

Processor and System-on-Chip Simulation

inferredcites →https://doi.org/10.1109/hpca.2005.17openalex-snapshot

Improving Multiple-CMP Systems Using Token Coherence

inferredcites →https://doi.org/10.1109/ispass.2009.4919636openalex-snapshot

GARNET: A detailed on-chip network model inside a full-system simulator

inferredcites →https://doi.org/10.1109/mm.2003.1196116openalex-snapshot

The AMD opteron processor for multiprocessor servers

inferredcites →https://doi.org/10.1109/mm.2006.82openalex-snapshot

The M5 Simulator: Modeling Networked Systems

inferredcites →https://doi.org/10.1145/1105734.1105747openalex-snapshot

Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset

inferredcites →https://doi.org/10.1145/1669112.1669172openalex-snapshot

McPAT

inferredcites →https://doi.org/10.1145/166955.166979openalex-snapshot

The Wisconsin Wind Tunnel: virtual prototyping of parallel computers

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

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Active Accelerated Self-healing as a Key Design Knob for Cross-Layer Resilience

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Aging Mitigation Techniques for Microprocessors Using Anti-aging Software

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Gradual Consistency Checking

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Learning-Based DRM and Energy Optimization for Manycore Dark Silicon Processors

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Extensible and Configurable RISC-V Based Virtual Prototype

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Closing Remarks and Open Questions

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Practical Multicore Extension of Functionally and Temporally Correct Real-Time Simulation for Automotive Systems

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inferred← citeshttps://doi.org/10.1007/978-3-030-47487-4_3openalex-snapshot

The Dynamic Random Access Memory Challenge in Embedded Computing Systems

inferred← citeshttps://doi.org/10.1007/978-3-030-47956-5_16openalex-snapshot

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inferred← citeshttps://doi.org/10.1007/978-3-030-48340-1_22openalex-snapshot

Multicore Performance Prediction – Comparing Three Recent Approaches in a Case Study

inferred← citeshttps://doi.org/10.1007/978-3-030-52017-5_11openalex-snapshot

Cross-Layer Resilience Against Soft Errors: Key Insights

inferred← citeshttps://doi.org/10.1007/978-3-030-52017-5_13openalex-snapshot

Reliability Analysis and Mitigation of Near-Threshold Voltage (NTC) Caches

inferred← citeshttps://doi.org/10.1007/978-3-030-52017-5_18openalex-snapshot

Design of Efficient, Dependable SoCs Based on a Cross-Layer-Reliability Approach with Emphasis on Wireless Communication as Application and DRAM Memories

inferred← citeshttps://doi.org/10.1007/978-3-030-52017-5_21openalex-snapshot

Exploiting Memory Resilience for Emerging Technologies: An Energy-Aware Resilience Exemplar for STT-RAM Memories

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ASTEROID and the Replica-Aware Co-scheduling for Mixed-Criticality

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Fault-Tolerant Computing with Heterogeneous Hardening Modes

inferred← citeshttps://doi.org/10.1007/978-3-030-52017-5_9openalex-snapshot

Lightweight Software-Defined Error Correction for Memories

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Investigating Transactional Memory for High Performance Embedded Systems

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Accelerating Inference on Binary Neural Networks with Digital RRAM Processing

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An Open-Source RISC-V Evaluation Platform

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Introduction

inferred← citeshttps://doi.org/10.1007/978-3-030-55704-1_3openalex-snapshot

Fault Injection Framework Using Virtual Platforms

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Co-designing OpenMP Features Using OMPT and Simulation Tools

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CoPTA: Contiguous Pattern Speculating TLB Architecture

inferred← citeshttps://doi.org/10.1007/978-3-030-60939-9_8openalex-snapshot

DRAMSys4.0: A Fast and Cycle-Accurate SystemC/TLM-Based DRAM Simulator

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Trustworthy System-on-Chip Design Using Secure on-Chip Communication Architectures

inferred← citeshttps://doi.org/10.1007/978-3-030-69131-8_10openalex-snapshot

Network-on-Chip Attack Detection using Machine Learning

inferred← citeshttps://doi.org/10.1007/978-3-030-69131-8_11openalex-snapshot

Trojan Aware Network-on-Chip Routing

inferred← citeshttps://doi.org/10.1007/978-3-030-69131-8_15openalex-snapshot

Securing Silicon Photonic NoCs Against Hardware Attacks

inferred← citeshttps://doi.org/10.1007/978-3-030-69131-8_2openalex-snapshot

Interconnect Modeling for Homogeneous and Heterogeneous Multiprocessors

inferred← citeshttps://doi.org/10.1007/978-3-030-69131-8_4openalex-snapshot

Lightweight Encryption Using Incremental Cryptography

inferred← citeshttps://doi.org/10.1007/978-3-030-69131-8_5openalex-snapshot

Trust-Aware Routing in NoC-Based SoCs

inferred← citeshttps://doi.org/10.1007/978-3-030-69131-8_6openalex-snapshot

Lightweight Anonymous Routing for On-chip Interconnects

inferred← citeshttps://doi.org/10.1007/978-3-030-69131-8_8openalex-snapshot

Real-Time Detection and Localization of DoS Attacks

inferred← citeshttps://doi.org/10.1007/978-3-030-69131-8_9openalex-snapshot

Securing on-Chip Communication Using Digital Watermarking

inferred← citeshttps://doi.org/10.1007/978-3-030-74536-3_4openalex-snapshot

Exploiting Reduced Voltage Margins: From Node- to the Datacenter-level

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A Hierarchical Task Scheduler for Heterogeneous Computing

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Graviton: A Reconfigurable Memory-Compute Fabric for Data Intensive Applications

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RAT: A Lightweight Architecture Independent System-Level Soft Error Mitigation Technique

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Evaluating Soft Error Mitigation Trade-offs During Early Design Stages

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Hardware-Assisted Online Data Race Detection

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A Proposal for Hybrid Memories Management Exploring Fuzzy-Based Page Migration Policy

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Interconnect Architectures for 3D Technologies

inferred← citeshttps://doi.org/10.1007/978-3-031-01753-7openalex-snapshot

Hardware and Software Support for Virtualization

inferred← citeshttps://doi.org/10.1007/978-3-031-02032-2_3openalex-snapshot

In–memory Data Encryption

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Accurate LLVM IR to Binary CFGs Mapping for Simulation of Optimized Embedded Software

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Rapid Execution Time Estimation for Heterogeneous Memory Systems Through Differential Tracing

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Eine Open-Source RISC-V Evaluierungsplattform

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Soft Error Assessment Methodology

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Protected Functions: User Space Privileged Function Calls

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CP$$^{3}$$: Hierarchical Cross-Platform Power/Performance Prediction Using a Transfer Learning Approach

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SAMVA: Static Analysis for Multi-fault Attack Paths Determination

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inferred← citeshttps://doi.org/10.1007/978-3-031-38579-7_11openalex-snapshot

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DeTAR: A Decision Tree-Based Adaptive Routing in Networks-on-Chip

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COMPESCE: A Co-design Approach for Memory Subsystem Performance Analysis in HPC Many-Cores

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TAPRE-HBM: Trace-Based Processor Rapid Emulation Using HBM on FPGAs

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parti-gem5: gem5’s Timing Mode Parallelised

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Unlocking the Potential of RISC-V Heterogeneous MPSoC: A PANACA-Based Approach to Simulation and Modeling

inferred← citeshttps://doi.org/10.1007/978-3-031-46077-7_3openalex-snapshot

NTHPC: Embracing Near-Threshold Operation for High Performance Multi-core Systems

inferred← citeshttps://doi.org/10.1007/978-3-031-48796-5_14openalex-snapshot

SearchGEM5: Towards Reliable Gem5 with Search Based Software Testing and Large Language Models

inferred← citeshttps://doi.org/10.1007/978-3-031-51692-4_3openalex-snapshot

Hardware and Environment Modeling

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Predicting GPU Kernel’s Performance on Upcoming Architectures

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VLASPH: Smoothed Particle Hydrodynamics on VLA SIMD Architectures

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Exploring Processor Micro-architectures Optimised for BLAS3 Micro-kernels

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A Leap of Confidence: A Write-Intensity Aware Prudent Page Migration for Hybrid Memories

inferred← citeshttps://doi.org/10.1007/978-3-031-73122-8_5openalex-snapshot

RISC-V Word-Size Modular Instructions for Residue Number Systems

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HW-EPOLL: Hardware-Assisted User Space Event Notification for Epoll Syscall

inferred← citeshttps://doi.org/10.1007/978-3-031-78380-7_6openalex-snapshot

A Novel System Simulation Framework for HBM2 FPGA Platforms

inferred← citeshttps://doi.org/10.1007/978-3-031-83093-8_6openalex-snapshot

Programmable Analysis of RISC-V Processors Using WAL

inferred← citeshttps://doi.org/10.1007/978-3-031-85700-3_1openalex-snapshot

RAVE: RISC-V Analyzer of Vector Executions, A QEMU Tracing Plugin

inferred← citeshttps://doi.org/10.1007/978-3-031-87345-4_19openalex-snapshot

A653MSim: An ARINC 653 Multicore Simulator

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Self-powered Embedded Systems: The Role of Non-volatile Memory Technology in IoT Devices

inferred← citeshttps://doi.org/10.1007/978-3-031-96473-2_25openalex-snapshot

SOT-MRAM Devices in Memory Hierarchy for Next-Generation Computing Systems

inferred← citeshttps://doi.org/10.1007/978-3-031-99854-6_1openalex-snapshot

Noise Injection for Performance Bottleneck Analysis

inferred← citeshttps://doi.org/10.1007/978-3-031-99857-7_1openalex-snapshot

SimPoint+: More Stable, Accurate and Efficient Program Analysis

inferred← citeshttps://doi.org/10.1007/978-3-032-00627-1_6openalex-snapshot

Fast and Efficient Secure L1 Caches for SMT

inferred← citeshttps://doi.org/10.1007/978-3-032-00627-1_7openalex-snapshot

FatPTE - Expanding Page Table Entries for Security

inferred← citeshttps://doi.org/10.1007/978-3-032-02436-7_6openalex-snapshot

Efficiently Exploiting Irregular Parallelism Using Keys at Scale

inferred← citeshttps://doi.org/10.1007/978-3-032-03281-2_24openalex-snapshot

Reduction of Average-Performance Degradation and Variance in Faulty CPU Cache Memories

inferred← citeshttps://doi.org/10.1007/978-3-032-03281-2_5openalex-snapshot

CHaOS: A Persistent Lightweight Cache Hybridization-Aware OS

inferred← citeshttps://doi.org/10.1007/978-3-032-06751-7_12openalex-snapshot

A New Cross-Product Instruction for RISC-V CPUs

inferred← citeshttps://doi.org/10.1007/978-3-032-06751-7_15openalex-snapshot

Efficiency of Parallel Machine Learning Algorithms on Multiprocessor and GPU Architectures

inferred← citeshttps://doi.org/10.1007/978-3-032-07612-0_42openalex-snapshot

Advancing the RISC-V Performance Simulation Ecosystem with Data Prefetching

inferred← citeshttps://doi.org/10.1007/978-3-032-09586-2_5openalex-snapshot

Deliberately Flipping Bits in Memristive Crossbar Arrays

inferred← citeshttps://doi.org/10.1007/978-3-032-20533-9_21openalex-snapshot

Network Latency Prediction on a 2D Distributed Shared Memory Multiprocessor

inferred← citeshttps://doi.org/10.1007/978-3-032-23871-9_1openalex-snapshot

A Framework for Automated Integration of High-Level Simulators in RISC-V SoCs

inferred← citeshttps://doi.org/10.1007/978-3-032-24804-6_45openalex-snapshot

Architectural Evaluation of Photonic Accelerators: Identifying System-Level Bottlenecks in GEMM Operations

inferred← citeshttps://doi.org/10.1007/978-3-032-24839-8_11openalex-snapshot

GreenMalloc: Allocator Optimisation for Industrial Workloads

inferred← citeshttps://doi.org/10.1007/978-3-032-35078-7_33openalex-snapshot

Comparative Analysis of CPU Emulation Techniques for Embedded and IoT Systems: A Performance Evaluation of Translation and Interpretation-Based Simulation in the Renode Framework

inferred← citeshttps://doi.org/10.1007/978-3-032-38692-2_9openalex-snapshot

Hardware Lazy PAT: Making Memory Encryption with Integrity Verification Unobtrusive

inferred← citeshttps://doi.org/10.1007/978-3-319-07518-1_3openalex-snapshot

Exascale Radio Astronomy: Can We Ride the Technology Wave?

inferred← citeshttps://doi.org/10.1007/978-3-319-08422-0_128openalex-snapshot

An Overview of Chip Multi-Processors Simulators Technology

inferred← citeshttps://doi.org/10.1007/978-3-319-11457-6_3openalex-snapshot

Simulation of Real-Time Multiprocessor Scheduling Using DES

inferred← citeshttps://doi.org/10.1007/978-3-319-14313-2_24openalex-snapshot

Improving Energy and Performance with Spintronics Caches in Multicore Systems

inferred← citeshttps://doi.org/10.1007/978-3-319-14325-5_45openalex-snapshot

An Automated Performance-Aware Approach to Reliability Transformations

inferred← citeshttps://doi.org/10.1007/978-3-319-18467-8_29openalex-snapshot

Mitigating Code-Reuse Attacks on CISC Architectures in a Hardware Approach

inferred← citeshttps://doi.org/10.1007/978-3-319-23216-4_4openalex-snapshot

Stable Matching Scheduler for Single-ISA Heterogeneous Multi-core Processors

inferred← citeshttps://doi.org/10.1007/978-3-319-25945-1_13openalex-snapshot

Test-Data Generation for Testing Parallel Real-Time Systems

inferred← citeshttps://doi.org/10.1007/978-3-319-27119-4_1openalex-snapshot

Parallelizing Block Cryptography Algorithms on Speculative Multicores

inferred← citeshttps://doi.org/10.1007/978-3-319-30695-7_28openalex-snapshot

Protecting Code Regions on Asymmetrically Reliable Caches

inferred← citeshttps://doi.org/10.1007/978-3-319-31295-8_7openalex-snapshot

Virtualization Guided Tsunami and Storm Surge Simulations for Low Power Architectures

inferred← citeshttps://doi.org/10.1007/978-3-319-31596-6_12openalex-snapshot

NoC-Aware Computational Sprinting

inferred← citeshttps://doi.org/10.1007/978-3-319-31596-6_5openalex-snapshot

Thermal Safe Power: Efficient Thermal-Aware Power Budgeting for Manycore Systems in Dark Silicon

inferred← citeshttps://doi.org/10.1007/978-3-319-31596-6_8openalex-snapshot

Robust Application Scheduling with Adaptive Parallelism in Dark-Silicon Constrained Multicore Systems

inferred← citeshttps://doi.org/10.1007/978-3-319-32094-6_4openalex-snapshot

Cycle-Accurate SDRAM Power Modeling

inferred← citeshttps://doi.org/10.1007/978-3-319-39589-0_13openalex-snapshot

Evaluating Out-of-Order Engine Limitations Using Uop Flow Simulation

inferred← citeshttps://doi.org/10.1007/978-3-319-40528-5_18openalex-snapshot

FFMK: A Fast and Fault-Tolerant Microkernel-Based System for Exascale Computing

inferred← citeshttps://doi.org/10.1007/978-3-319-44802-2_3openalex-snapshot

A Maude Framework for Cache Coherent Multicore Architectures

inferred← citeshttps://doi.org/10.1007/978-3-319-46079-6_1openalex-snapshot

Behavioral Emulation for Scalable Design-Space Exploration of Algorithms and Architectures

inferred← citeshttps://doi.org/10.1007/978-3-319-46301-8_38openalex-snapshot

Intra-CPU Traffic Estimation and Implications on Networks-on-Chip Research

inferred← citeshttps://doi.org/10.1007/978-3-319-46535-7_2openalex-snapshot

Memory Analysis and Performance Modeling for HPC Applications on Embedded Hardware via Instruction Accurate Simulation

inferred← citeshttps://doi.org/10.1007/978-3-319-50688-3_13openalex-snapshot

Fundamentals of Graphene-Enabled Wireless On-Chip Networking

inferred← citeshttps://doi.org/10.1007/978-3-319-51735-3_3openalex-snapshot

SSDExplorer: A Virtual Platform for SSD Simulations

inferred← citeshttps://doi.org/10.1007/978-3-319-54999-6_17openalex-snapshot

DVFS Space Exploration in Power Constrained Processing-in-Memory Systems

inferred← citeshttps://doi.org/10.1007/978-3-319-54999-6_9openalex-snapshot

A Method for Fast Evaluation of Sharing Set Management Strategies in Cache Coherence Protocols

inferred← citeshttps://doi.org/10.1007/978-3-319-55345-0_5openalex-snapshot

Redesigning Software and Systems for Nonvolatile Processors on Self-Powered Devices

inferred← citeshttps://doi.org/10.1007/978-3-319-56258-2_27openalex-snapshot

A Machine Learning Methodology for Cache Recommendation

inferred← citeshttps://doi.org/10.1007/978-3-319-66176-6_6openalex-snapshot

Factor-Based C-AMAT Analysis for Memory Optimization

inferred← citeshttps://doi.org/10.1007/978-3-319-67630-2_10openalex-snapshot

Towards an Integrated Strategy to Preserve Digital Computing Performance Scaling Using Emerging Technologies

inferred← citeshttps://doi.org/10.1007/978-3-319-68034-7_4openalex-snapshot

A Formal Model of Parallel Execution on Multicore Architectures with Multilevel Caches

inferred← citeshttps://doi.org/10.1007/978-3-319-68210-5_8openalex-snapshot

Improving Branch Prediction for Thread Migration on Multi-core Architectures

inferred← citeshttps://doi.org/10.1007/978-3-319-68783-4_31openalex-snapshot

Efficient Subgraph Matching on Non-volatile Memory

inferred← citeshttps://doi.org/10.1007/978-3-319-72598-7_19openalex-snapshot

Performance Attacks on Branch Predictors in Embedded Processors with SMT Support

inferred← citeshttps://doi.org/10.1007/978-3-319-73830-7_15openalex-snapshot

Research on Optimizing Last Level Cache Performance for Hybrid Main Memory

inferred← citeshttps://doi.org/10.1007/978-3-319-77479-4_10openalex-snapshot

Energy-Efficient Task-to-Core Assignment for Heterogeneous Clustered Manycores

inferred← citeshttps://doi.org/10.1007/978-3-319-77479-4_2openalex-snapshot

Background and Related Work

inferred← citeshttps://doi.org/10.1007/978-3-319-77479-4_3openalex-snapshot

System Model

inferred← citeshttps://doi.org/10.1007/978-3-319-77479-4_4openalex-snapshot

Experimental Framework

inferred← citeshttps://doi.org/10.1007/978-3-319-77479-4_8openalex-snapshot

Energy and Peak Power Efficiency Analysis for Simple Approximation Schemes

inferred← citeshttps://doi.org/10.1007/978-3-319-77610-1_12openalex-snapshot

Redundant Execution on Heterogeneous Multi-cores Utilizing Transactional Memory

inferred← citeshttps://doi.org/10.1007/978-3-319-77610-1_16openalex-snapshot

A Tightly Coupled Heterogeneous Core with Highly Efficient Low-Power Mode

inferred← citeshttps://doi.org/10.1007/978-3-319-77610-1_7openalex-snapshot

A Hybrid Approach for Runtime Analysis Using a Cycle and Instruction Accurate Model

inferred← citeshttps://doi.org/10.1007/978-3-319-90385-9_5openalex-snapshot

The Processing-in-Memory Paradigm: Mechanisms to Enable Adoption

inferred← citeshttps://doi.org/10.1007/978-3-319-91074-1_4openalex-snapshot

State-of-the-Art Sharing-Aware Mapping Methods

inferred← citeshttps://doi.org/10.1007/978-3-319-91734-4_30openalex-snapshot

Models of Architecture for DSP Systems

inferred← citeshttps://doi.org/10.1007/978-3-319-91962-1_11openalex-snapshot

Proof-of-Concept HARPA Measurement-Based Platform Modelling Framework

inferred← citeshttps://doi.org/10.1007/978-3-319-91962-1_3openalex-snapshot

Aging Effects: From Physics to CAD

inferred← citeshttps://doi.org/10.1007/978-3-319-91962-1_9openalex-snapshot

Monitor and Knob Techniques in Network-on-Chip Architectures

inferred← citeshttps://doi.org/10.1007/978-3-319-92040-5_16openalex-snapshot

Packetization of Shared-Memory Traces for Message Passing Oriented NoC Simulation

inferred← citeshttps://doi.org/10.1007/978-3-319-92040-5_7openalex-snapshot

Compiler-Assisted Source-to-Source Skeletonization of Application Models for System Simulation

inferred← citeshttps://doi.org/10.1007/978-3-319-98116-1_9openalex-snapshot

Test Generation and Lightweight Checking for Multi-core Memory Consistency

inferred← citeshttps://doi.org/10.1007/978-3-642-28365-9_4openalex-snapshot

Exploiting Both Pipelining and Data Parallelism with SIMD Reconfigurable Architecture

inferred← citeshttps://doi.org/10.1007/978-3-642-35898-2_19openalex-snapshot

Efficient Broadcast Scheme Based on Sub-network Partition for Many-Core CMPs on Gem5 Simulator

inferred← citeshttps://doi.org/10.1007/978-3-642-35898-2_6openalex-snapshot

Design and Implementation of Dynamically Reconfigurable Token Coherence Protocol for Many-Core Processor

inferred← citeshttps://doi.org/10.1007/978-3-642-36424-2_18openalex-snapshot

An Application-Aware Cache Replacement Policy for Last-Level Caches

inferred← citeshttps://doi.org/10.1007/978-3-642-40820-5_22openalex-snapshot

Asymmetry-Aware Scheduling in Heterogeneous Multi-core Architectures

inferred← citeshttps://doi.org/10.1007/978-3-642-40820-5_3openalex-snapshot

Extracting Threaded Traces in Simulation Environments

inferred← citeshttps://doi.org/10.1007/978-3-642-41635-4_21openalex-snapshot

Reconfigurable Many-Core Processor with Cache Coherence

inferred← citeshttps://doi.org/10.1007/978-3-642-45293-2_18openalex-snapshot

An Efficient Parallel Mechanism for Highly-Debuggable Multicore Simulator

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