On the public citation graph
IBM Power Edge of Network Processor: A Wire-Speed System on a Chip
0 signed · 47 inferred · view as graph
Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.
Is this your work? Sign in with ORCID and put your name on the
claims that are yours.
Reference health. See whether every reference in this work resolves to a
known work and none has been retracted — and get a dated CiteStamped
badge you can embed.
What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1109/infocom.2006.204openalex-snapshot
High-Performance Pattern-Matching for Intrusion Detection
inferredcites →https://doi.org/10.1109/isca.1995.524578openalex-snapshot
Simultaneous multithreading: Maximizing on-chip parallelism
inferredcites →https://doi.org/10.1147/jrd.2009.2036972openalex-snapshot
Workload and network-optimized computing systems
inferredcites →https://doi.org/10.4242/balisagevol4.salz01openalex-snapshot
Hardware and software trade-offs in the IBM DataPower XML XG4 processor card
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/s11390-015-1507-4openalex-snapshot
Adapting Memory Hierarchies for Emerging Datacenter Interconnects
inferred← citeshttps://doi.org/10.1016/j.comcom.2013.03.002openalex-snapshot
A memory-based NFA regular expression match engine for signature-based intrusion detection
inferred← citeshttps://doi.org/10.1016/j.comcom.2014.04.006openalex-snapshot
IP address lookup using bit-shuffled trie
inferred← citeshttps://doi.org/10.1016/j.parco.2017.01.003openalex-snapshot
TCASM: An asynchronous shared memory interface for high-performance application composition
inferred← citeshttps://doi.org/10.1093/comjnl/bxs093openalex-snapshot
Multi-Stride String Searching for High-Speed Content Inspection
inferred← citeshttps://doi.org/10.1093/comjnl/bxu079openalex-snapshot
Hardware Accelerator to Detect Multi-Segment Virus Patterns
inferred← citeshttps://doi.org/10.1109/access.2023.3329984openalex-snapshot
Review of Memory RAS for Data Centers
inferred← citeshttps://doi.org/10.1109/hipc.2014.7116709openalex-snapshot
Matrix-matrix multiplication on a large register file architecture with indirection
inferred← citeshttps://doi.org/10.1109/hpca.2012.6169044openalex-snapshot
Accelerating business analytics applications
inferred← citeshttps://doi.org/10.1109/hpca.2016.7446051openalex-snapshot
Pushing the limits of accelerator efficiency while retaining programmability
inferred← citeshttps://doi.org/10.1109/icassp.2013.6638161openalex-snapshot
Processor architecture for software implementation of multi-sector G-RAKE receivers for HSUPA wireless infrastructure
inferred← citeshttps://doi.org/10.1109/iccd.2013.6657021openalex-snapshot
Characterizing the costs and benefits of hardware parallelism in accelerator cores
inferred← citeshttps://doi.org/10.1109/ipdpsw.2019.00016openalex-snapshot
Programmable Acceleration for Sparse Matrices in a Data-Movement Limited World
inferred← citeshttps://doi.org/10.1109/ispass.2013.6557152openalex-snapshot
Evaluating cache coherent shared virtual memory for heterogeneous multicore chips
inferred← citeshttps://doi.org/10.1109/jiot.2020.3027418openalex-snapshot
Intelligent Charging Path Planning for IoT Network Over Blockchain-Based Edge Architecture
inferred← citeshttps://doi.org/10.1109/l-ca.2012.29openalex-snapshot
Accelerator Memory Reuse in the Dark Silicon Era
inferred← citeshttps://doi.org/10.1109/mcsoc.2013.34openalex-snapshot
GPU-based Multi-stream Analyzer on Application Layer for Service-Oriented Router
inferred← citeshttps://doi.org/10.1109/micro.2012.49openalex-snapshot
Designing a Programmable Wire-Speed Regular-Expression Matching Accelerator
inferred← citeshttps://doi.org/10.1109/socc.2012.6398390openalex-snapshot
Ventti: A vertically integrated framework for simulation and optimization of networks-on-Chip
inferred← citeshttps://doi.org/10.1109/tcad.2015.2481796openalex-snapshot
Accelerating Architectural Simulation Via Statistical Techniques: A Survey
inferred← citeshttps://doi.org/10.1109/tcad.2017.2706562openalex-snapshot
A Template-Based Design Methodology for Graph-Parallel Hardware Accelerators
inferred← citeshttps://doi.org/10.1109/tnsm.2014.2346078openalex-snapshot
OpenFlow in the Small: A Flexible and Efficient Network Acceleration Framework for Multi-Core Systems
inferred← citeshttps://doi.org/10.1145/2370816.2370872openalex-snapshot
Hardware acceleration in the IBM PowerEN processor
inferred← citeshttps://doi.org/10.1145/2485922.2485933openalex-snapshot
Improving virtualization in the presence of software managed translation lookaside buffers
inferred← citeshttps://doi.org/10.1145/2508148.2485933openalex-snapshot
Improving virtualization in the presence of software managed translation lookaside buffers
inferred← citeshttps://doi.org/10.1145/2535372.2535412openalex-snapshot
On limitations of network acceleration
inferred← citeshttps://doi.org/10.1145/2588888openalex-snapshot
Architecture and Performance of the Hardware Accelerators in IBM’s PowerEN Processor
inferred← citeshttps://doi.org/10.1145/2660249openalex-snapshot
A methodology for automatic generation of executable communication specifications from parallel MPI applications
inferred← citeshttps://doi.org/10.1145/2906363.2907053openalex-snapshot
Scalable DFA Compilation for High-Performance Regular-Expression Matching
inferred← citeshttps://doi.org/10.1145/3476982openalex-snapshot
CICERO: A Domain-Specific Architecture for Efficient Regular Expression Matching
inferred← citeshttps://doi.org/10.1145/3672198.3673804openalex-snapshot
OmNICCL: Zero-cost Sparse AllReduce with Direct Cache Access and SmartNICs
inferred← citeshttps://doi.org/10.1147/jrd.2014.2380272openalex-snapshot
Debugging post-silicon fails in the IBM POWER8 bring-up lab
inferred← citeshttps://doi.org/10.17918/etd-6374openalex-snapshot
Instrumenting and analyzing platform-independent communication in applications
inferred← citeshttps://doi.org/10.5555/3195638.3195692openalex-snapshot
HARE: hardware accelerator for regular expressions
inferred← citeshttps://doi.org/10.5821/dissertation-2117-95109openalex-snapshot
Performance and power optimizations in chip multiprocessors for throughput-aware computation
inferred← citeshttps://doi.org/10.70675/c7c2b786z3986z4edez945fzcd4d3a382f16openalex-snapshot
Exploiting heterogeneous many cores on sequential code
Editorial review for independent work. ICSAC — the Institute for Complexity
Science and Advanced Computing — runs a structured editorial panel for researchers
publishing outside journals, and publishes on CiteStamp rails. Submission is free
and goes through ORCID: icsacinstitute.org/submit.