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Scope-Aware Data Cache Analysis for WCET Estimation

https://doi.org/10.1109/rtas.2011.27

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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/bfb0057777openalex-snapshot

On predicting data cache behavior for real-time systems

inferredcites →https://doi.org/10.1007/s11241-007-9032-3openalex-snapshot

Timing predictability of cache replacement policies

inferredcites →https://doi.org/10.1016/j.scico.2007.01.014openalex-snapshot

Chronos: A timing analyzer for embedded software

inferredcites →https://doi.org/10.1023/a:1008141130870openalex-snapshot

Fast and Precise WCET Prediction by Separated Cache and Path Analyses

inferredcites →https://doi.org/10.1023/a:1008190423977openalex-snapshot

Timing Analysis for Data and Wrap-Around Fill Caches

inferredcites →https://doi.org/10.1109/2.596622openalex-snapshot

When caches aren't enough: data prefetching techniques

inferredcites →https://doi.org/10.1109/32.392980openalex-snapshot

An accurate worst case timing analysis for RISC processors

inferredcites →https://doi.org/10.1109/ecrts.2006.33openalex-snapshot

Worst case timing analysis of input dependent data cache behavior

inferredcites →https://doi.org/10.1109/ecrts.2008.34openalex-snapshot

Improving the First-Miss Computation in Set-Associative Instruction Caches

inferredcites →https://doi.org/10.1109/real.1996.563722openalex-snapshot

Cache modeling for real-time software: beyond direct mapped instruction caches

inferredcites →https://doi.org/10.1109/real.2004.33openalex-snapshot

Modeling Out-of-Order Processors for Software Timing Analysis

inferredcites →https://doi.org/10.1109/rtas.2005.12openalex-snapshot

Bounding Worst-Case Data Cache Behavior by Analytically Deriving Cache Reference Patterns

inferredcites →https://doi.org/10.1109/rtas.2011.27openalex-snapshot

Scope-Aware Data Cache Analysis for WCET Estimation

inferredcites →https://doi.org/10.1109/rtss.2009.20openalex-snapshot

Unified Cache Modeling for WCET Analysis and Layout Optimizations

inferredcites →https://doi.org/10.1109/rtss.2010.8openalex-snapshot

A More Precise Abstract Domain for Multi-level Caches for Tighter WCET Analysis

inferredcites →https://doi.org/10.1109/rttas.1996.509540openalex-snapshot

Efficient worst case timing analysis of data caching

inferredcites →https://doi.org/10.1145/115952.115958openalex-snapshot

An architecture for software-controlled data prefetching

inferredcites →https://doi.org/10.1145/1289927.1289960openalex-snapshot

WCET estimation for executables in the presence of data caches

inferredcites →https://doi.org/10.1145/1457246.1457253openalex-snapshot

Analyzing the worst-case execution time for instruction caches with prefetching

inferredcites →https://doi.org/10.1145/1811212.1811220openalex-snapshot

Modeling shared cache and bus in multi-cores for timing analysis

inferredcites →https://doi.org/10.1145/268806.268810openalex-snapshot

The SimpleScalar tool set, version 2.0

inferredcites →https://doi.org/10.1145/325478.325479openalex-snapshot

Cache miss equations

inferredcites →https://doi.org/10.1145/378795.378859openalex-snapshot

Exact analysis of the cache behavior of nested loops

inferredcites →https://doi.org/10.4230/oasics.wcet.2006.671openalex-snapshot

A Definition and Classification of Timing Anomalies

inferredcites →https://doi.org/10.4230/oasics.wcet.2009.2283openalex-snapshot

WCET Analysis of Multi-Level Set-Associative Data Caches

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

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Symbolic Predictive Cache Analysis for Out-of-Order Execution

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MRU Cache Analysis for WCET Estimation

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FIFO Cache Analysis for WCET Estimation

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Analyzing Preemptive Global Scheduling

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Parametric Utilization Bounds

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Path Sensitive Cache Analysis Using Cache Miss Paths

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Data-Dependent WAR Analysis for Efficient Task-Based Intermittent Computing

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Interference-aware fixed-priority schedulability analysis on multiprocessors

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Fault-tolerant and real-time scheduling for mixed-criticality systems

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Response-time analysis for fixed-priority systems with a write-back cache

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Precise, efficient, and context-sensitive cache analysis

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Scope-aware data cache analysis for OpenMP programs on multi-core processors

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A generic framework to integrate data caches in the WCET analysis of real-time systems

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Automatic Safe Data Reuse Detection for the WCET Analysis of Systems With Data Caches

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Precise micro-architectural modeling for WCET analysis via AI+SAT

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Work in Progress: Reducing WCET Estimation by Increasing the Number of Persistent Blocks

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Scalable and Precise Refinement of Cache Timing Analysis via Model Checking

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