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Timing Analysis for Resource Access Interference on Adaptive Resource Arbiters

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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/s10009-006-0019-5openalex-snapshot
System architecture evaluation using modular performance analysis: a case study
inferredcites →https://doi.org/10.1007/s11241-007-9040-3openalex-snapshot
Timing analysis of the FlexRay communication protocol
inferredcites →https://doi.org/10.1109/dac.2007.375165openalex-snapshot
The Case for the Precision Timed (PRET) Machine
inferredcites →https://doi.org/10.1109/date.2010.5456951openalex-snapshot
Bounding the shared resource load for the performance analysis of multiprocessor systems
inferredcites →https://doi.org/10.1109/date.2010.5456952openalex-snapshot
Worst case delay analysis for memory interference in multicore systems
inferredcites →https://doi.org/10.1109/date.2010.5457184openalex-snapshot
Integrated end-to-end timing analysis of networked AUTOSAR-compliant systems
inferredcites →https://doi.org/10.1109/rtas.2010.24openalex-snapshot
Timing Analysis for TDMA Arbitration in Resource Sharing Systems
inferredcites →https://doi.org/10.1109/rtss.2007.13openalex-snapshot
Distributed Minimal Time Convergecast Scheduling for Small or Sparse Data Sources
inferredcites →https://doi.org/10.1109/rtss.2007.24openalex-snapshot
Bus Access Optimization for Predictable Implementation of Real-Time Applications on Multiprocessor Systems-on-Chip
inferredcites →https://doi.org/10.1109/rtss.2009.32openalex-snapshot
Timing Analysis of Concurrent Programs Running on Shared Cache Multi-Cores
inferredcites →https://doi.org/10.1109/tc.2009.156openalex-snapshot
Impact of Peripheral-Processor Interference on WCET Analysis of Real-Time Embedded Systems
inferredcites →https://doi.org/10.1109/tcad.2009.2013287openalex-snapshot
Memory Hierarchies, Pipelines, and Buses for Future Architectures in Time-Critical Embedded Systems
inferredcites →https://doi.org/10.1145/1278480.1278545openalex-snapshot
The case for the precision timed (PRET) machine
inferredcites →https://doi.org/10.1145/1450135.1450172openalex-snapshot
Reliable performance analysis of a multicore multithreaded system-on-chip
inferredcites →https://doi.org/10.1145/1629335.1629369openalex-snapshot
Cache-aware scheduling and analysis for multicores
inferredcites →https://doi.org/10.1145/1774088.1774162openalex-snapshot
Performance analysis of FlexRay-based systems using real-time calculus, revisited
inferredcites →https://doi.org/10.5555/1870926.1871105openalex-snapshot
Worst case delay analysis for memory interference in multicore systems
inferredcites →https://doi.org/10.5555/1870926.1871108openalex-snapshot
Bounding the shared resource load for the performance analysis of multiprocessor systems

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

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Impact of Resource Sharing on Performance and Performance Prediction: A Survey
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Causality problem in real-time calculus
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An extensible framework for multicore response time analysis
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Design and analysis of SIC: a provably timing-predictable pipelined processor core
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A formal framework to design and prove trustworthy memory controllers
inferred← citeshttps://doi.org/10.1016/j.sysarc.2015.04.005openalex-snapshot
State-based real-time analysis of SDF applications on MPSoCs with shared communication resources
inferred← citeshttps://doi.org/10.1109/cpsna.2015.24openalex-snapshot
MEDUSA: A Predictable and High-Performance DRAM Controller for Multicore Based Embedded Systems
inferred← citeshttps://doi.org/10.1109/ecrts.2012.32openalex-snapshot
Memory Access Control in Multiprocessor for Real-Time Systems with Mixed Criticality
inferred← citeshttps://doi.org/10.1109/ecrts.2016.19openalex-snapshot
A Framework for the Derivation of WCET Analyses for Multi-core Processors
inferred← citeshttps://doi.org/10.1109/emsoft.2013.6658595openalex-snapshot
Scheduling of mixed-criticality applications on resource-sharing multicore systems
inferred← citeshttps://doi.org/10.1109/etfa.2011.6059176openalex-snapshot
WCET analysis considering contention on memory bus in COTS-based multicores
inferred← citeshttps://doi.org/10.1109/hpcc.2012.212openalex-snapshot
An Analysis of the Impact of Bus Contention on the WCET in Multicores
inferred← citeshttps://doi.org/10.1109/isorc.2015.43openalex-snapshot
Seeking Time-Composable Partitions of Tasks for COTS Multicore Processors
inferred← citeshttps://doi.org/10.1109/rtas.2016.7461339openalex-snapshot
Memory Servers for Multicore Systems
inferred← citeshttps://doi.org/10.1109/rtas.2018.00026openalex-snapshot
Shared-Resource-Centric Limited Preemptive Scheduling: A Comprehensive Study of Suspension-Based Partitioning Approaches
inferred← citeshttps://doi.org/10.1109/rtas.2019.00031openalex-snapshot
Multiprocessor Synchronization of Periodic Real-Time Tasks Using Dependency Graphs
inferred← citeshttps://doi.org/10.1109/rtas.2019.00036openalex-snapshot
Holistic Resource Allocation for Multicore Real-Time Systems
inferred← citeshttps://doi.org/10.1109/rtas52030.2021.00024openalex-snapshot
DNA: Dynamic Resource Allocation for Soft Real-Time Multicore Systems
inferred← citeshttps://doi.org/10.1109/rtcsa.2012.48openalex-snapshot
Memory-Aware Scheduling of Multicore Task Sets for Real-Time Systems
inferred← citeshttps://doi.org/10.1109/rtcsa.2013.6732203openalex-snapshot
Timing analysis of PCM main memory in multicore systems
inferred← citeshttps://doi.org/10.1109/rtss.2013.44openalex-snapshot
Worst Case Analysis of DRAM Latency in Multi-requestor Systems
inferred← citeshttps://doi.org/10.1109/rtss.2018.00060openalex-snapshot
Design and Analysis of SIC: A Provably Timing-Predictable Pipelined Processor Core
inferred← citeshttps://doi.org/10.1109/rtss46320.2019.00031openalex-snapshot
Improving Prediction Accuracy of Memory Interferences for Multicore Platforms
inferred← citeshttps://doi.org/10.1109/sies.2013.6601469openalex-snapshot
Identifying the sources of unpredictability in COTS-based multicore systems
inferred← citeshttps://doi.org/10.1109/tc.2015.2425874openalex-snapshot
Schedulability Analysis for Memory Bandwidth Regulated Multicore Real-Time Systems
inferred← citeshttps://doi.org/10.1109/trustcom.2011.146openalex-snapshot
Response Time Analysis of COTS-Based Multicores Considering the Contention on the Shared Memory Bus
inferred← citeshttps://doi.org/10.1145/2380356.2380372openalex-snapshot
Timed model checking with abstractions
inferred← citeshttps://doi.org/10.1145/2500886openalex-snapshot
Computation takes time, but how much?
inferred← citeshttps://doi.org/10.1145/2656045.2656063openalex-snapshot
Parallel many-core avionics systems
inferred← citeshttps://doi.org/10.1145/2752801.2752805openalex-snapshot
Towards compositionality in execution time analysis
inferred← citeshttps://doi.org/10.1145/2834848.2834862openalex-snapshot
A generic and compositional framework for multicore response time analysis
inferred← citeshttps://doi.org/10.1145/2834848.2834872openalex-snapshot
WCET analysis for multi-core processors with shared buses and event-driven bus arbitration
inferred← citeshttps://doi.org/10.1145/2997465.2997471openalex-snapshot
Enabling Compositionality for Multicore Timing Analysis
inferred← citeshttps://doi.org/10.1145/3323212openalex-snapshot
A Survey of Timing Verification Techniques for Multi-Core Real-Time Systems
inferred← citeshttps://doi.org/10.1145/3534879.3534907openalex-snapshot
A Coq Framework for More Trustworthy DRAM Controllers
inferred← citeshttps://doi.org/10.1145/3591594openalex-snapshot
Synchronous Deterministic Parallel Programming for Multi-Cores with ForeC
inferred← citeshttps://doi.org/10.24382/1941openalex-snapshot
Improved Composability of Software Components through Parallel Hardware Platforms for In-Car Multimedia Systems
inferred← citeshttps://doi.org/10.3929/ethz-a-006395820openalex-snapshot
Efficiency and predictability in resource sharing multicore systems
inferred← citeshttps://doi.org/10.4230/oasics.wcet.2014.31openalex-snapshot
Contention in Multicore Hardware Shared Resources: Understanding of the State of the Art
inferred← citeshttps://doi.org/10.4230/oasics.wcet.2015.11openalex-snapshot
Software-enforced Interconnect Arbitration for COTS Multicores
inferred← citeshttps://doi.org/10.5555/2555754.2555771openalex-snapshot
Scheduling of mixed-criticality applications on resource-sharing multicore systems
inferred← citeshttps://doi.org/10.5555/2616606.2616724openalex-snapshot
Impact of resource sharing on performance and performance prediction
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A time-predictable many-core processor design for critical real-time embedded systems
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Enhancing timing analysis for COTS multicores for safety-related industry : a software approach
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Response time analysis of parameterized dataflow applications on heterogeneous SW/HW systems
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CoqDRAM - A Foundation for Designing Formally Proven Memory Controllers
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Caractérisation de la sensibilité aux interférences mémoire dans les systèmes temps-réels embarqués sur des plateformes multi-coeurs
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