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Memory-Aware Scheduling of Multicore Task Sets for Real-Time Systems
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/978-1-4615-4000-7_3openalex-snapshot
Synchronization in Multiple Processor Systems
inferredcites →https://doi.org/10.1007/s11241-005-0507-9openalex-snapshot
Measuring the Performance of Schedulability Tests
inferredcites →https://doi.org/10.1007/s11241-012-9158-9openalex-snapshot
Memory-centric scheduling for multicore hard real-time systems
inferredcites →https://doi.org/10.1016/b978-155860702-6/50016-8openalex-snapshot
Scheduling Algorithms for Multiprogramming in a Hard-Real-Time Environment
inferredcites →https://doi.org/10.1109/12.57058openalex-snapshot
Priority inheritance protocols: an approach to real-time synchronization
inferredcites →https://doi.org/10.1109/cgo.2004.1281665openalex-snapshot
LLVM: a compilation framework for lifelong program analysis & transformation
inferredcites →https://doi.org/10.1109/date.2010.5456952openalex-snapshot
Worst case delay analysis for memory interference in multicore systems
inferredcites →https://doi.org/10.1109/ecrts.2009.13openalex-snapshot
On the Design and Implementation of a Cache-Aware Multicore Real-Time Scheduler
inferredcites →https://doi.org/10.1109/les.2010.2041634openalex-snapshot
An Analyzable Memory Controller for Hard Real-Time CMPs
inferredcites →https://doi.org/10.1109/mm.2009.74openalex-snapshot
A Benchmark Characterization of the EEMBC Benchmark Suite
inferredcites →https://doi.org/10.1109/real.2002.1181569openalex-snapshot
Soft real-time scheduling on simultaneous multithreaded processors
inferredcites →https://doi.org/10.1109/rtas.2006.35openalex-snapshot
Real-Time Scheduling on Multicore Platforms
inferredcites →https://doi.org/10.1109/rtas.2011.28openalex-snapshot
Timing Analysis for Resource Access Interference on Adaptive Resource Arbiters
inferredcites →https://doi.org/10.1109/rtas.2011.33openalex-snapshot
A Predictable Execution Model for COTS-Based Embedded Systems
inferredcites →https://doi.org/10.1109/rtcsa.2006.31openalex-snapshot
Extended U-Link Scheduling to Increase the Execution Efficiency for SMT Real-Time Systems
inferredcites →https://doi.org/10.1109/rtcsa.2007.8openalex-snapshot
A Flexible Real-Time Locking Protocol for Multiprocessors
inferredcites →https://doi.org/10.1109/rtss.2007.13openalex-snapshot
Distributed Minimal Time Convergecast Scheduling for Small or Sparse Data Sources
inferredcites →https://doi.org/10.1109/rtss.2007.24openalex-snapshot
Bus Access Optimization for Predictable Implementation of Real-Time Applications on Multiprocessor Systems-on-Chip
inferredcites →https://doi.org/10.1109/rtss.2010.17openalex-snapshot
Optimality Results for Multiprocessor Real-Time Locking
inferredcites →https://doi.org/10.1109/rtss.2011.16openalex-snapshot
Soft Real-Time on Multiprocessors: Are Analysis-Based Schedulers Really Worth It?
inferredcites →https://doi.org/10.1109/rttas.1997.601360openalex-snapshot
OS-controlled cache predictability for real-time systems
inferredcites →https://doi.org/10.1145/1278480.1278545openalex-snapshot
The case for the precision timed (PRET) machine
inferredcites →https://doi.org/10.1145/1555754.1555764openalex-snapshot
Hardware support for WCET analysis of hard real-time multicore systems
inferredcites →https://doi.org/10.1145/1629335.1629369openalex-snapshot
Cache-aware scheduling and analysis for multicores
inferredcites →https://doi.org/10.1145/1629335.1629371openalex-snapshot
Implementing time-predictable load and store operations
inferredcites →https://doi.org/10.1145/1978802.1978814openalex-snapshot
A survey of hard real-time scheduling for multiprocessor systems
inferredcites →https://doi.org/10.1145/321738.321743openalex-snapshot
Scheduling Algorithms for Multiprogramming in a Hard-Real-Time Environment
inferredcites →https://doi.org/10.3233/emc-2005-00052openalex-snapshot
Adapting Pfair scheduling for symmetric multiprocessors
inferredcites →https://doi.org/10.5555/1870926.1871105openalex-snapshot
Worst case delay analysis for memory interference in multicore systems
inferredcites →https://doi.org/10.5555/200781.200792openalex-snapshot
Software-based cache partitioning for real-time applications
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-3-031-43943-8_3openalex-snapshot
Memory-Aware Latency Prediction Model for Concurrent Kernels in Partitionable GPUs: Simulations and Experiments
inferred← citeshttps://doi.org/10.1007/978-3-319-77610-1_4openalex-snapshot
Closed Loop Controller for Multicore Real-Time Systems
inferred← citeshttps://doi.org/10.1007/s11241-014-9211-yopenalex-snapshot
A formal approach to the WCRT analysis of multicore systems with memory contention under phase-structured task sets
inferred← citeshttps://doi.org/10.1016/j.compeleceng.2016.07.001openalex-snapshot
An effective approach to schedule time reduction on multi-core embedded systems
inferred← citeshttps://doi.org/10.1016/j.parco.2018.11.002openalex-snapshot
Combining PREM compilation and static scheduling for high-performance and predictable MPSoC execution
inferred← citeshttps://doi.org/10.1109/ccdc.2015.7161776openalex-snapshot
A task scheduling model and method for control-oriented multicore systems
inferred← citeshttps://doi.org/10.1109/dasc.2017.8101991openalex-snapshot
Dynamic interference quantification for multicore processors
inferred← citeshttps://doi.org/10.1109/dcas.2015.7356603openalex-snapshot
A genetic algorithm based approach to pipelined memory-aware scheduling on an MPSoC
inferred← citeshttps://doi.org/10.1109/ecrts.2013.28openalex-snapshot
A Dynamic Scratchpad Memory Unit for Predictable Real-Time Embedded Systems
inferred← citeshttps://doi.org/10.1109/edis57230.2022.9996534openalex-snapshot
Toward memory-centric scheduling for PREM task on multicore platforms, when processor assignments are specified
inferred← citeshttps://doi.org/10.1109/etfa.2015.7301431openalex-snapshot
Compositional analysis for the Multi-Resource Server
inferred← citeshttps://doi.org/10.1109/rtas.2014.6925986openalex-snapshot
The Multi-Resource Server for predictable execution on multi-core platforms
inferred← citeshttps://doi.org/10.1109/rtas.2019.00031openalex-snapshot
Multiprocessor Synchronization of Periodic Real-Time Tasks Using Dependency Graphs
inferred← citeshttps://doi.org/10.1109/rtas48715.2020.00005openalex-snapshot
Bringing Inter-Thread Cache Benefits to Federated Scheduling
inferred← citeshttps://doi.org/10.1109/rtest.2015.7369851openalex-snapshot
A memory-centric approach to enable timing-predictability within embedded many-core accelerators
inferred← citeshttps://doi.org/10.1109/rtss.2018.00048openalex-snapshot
BUNDLEP: Prioritizing Conflict Free Regions in Multi-threaded Programs to Improve Cache Reuse
inferred← citeshttps://doi.org/10.1109/rtss49844.2020.00034openalex-snapshot
A study of predictable execution models implementation for industrial data-flow applications on a multi-core platform with shared banked memory
inferred← citeshttps://doi.org/10.1109/rtss55097.2022.00039openalex-snapshot
Enabling GPU Memory Oversubscription via Transparent Paging to an NVMe SSD
inferred← citeshttps://doi.org/10.1109/rtss59052.2023.00030openalex-snapshot
Co-Located Parallel Scheduling of Threads to Optimize Cache Sharing
inferred← citeshttps://doi.org/10.1109/tc.2015.2500572openalex-snapshot
Global Real-Time Memory-Centric Scheduling for Multicore Systems
inferred← citeshttps://doi.org/10.1109/tc.2016.2614819openalex-snapshot
Exact Response Time Analysis for Fixed Priority Memory-Processor Co-Scheduling
inferred← citeshttps://doi.org/10.1142/s0218126617500426openalex-snapshot
Pipelined-Scheduling of Multiple Embedded Applications on a Multi-Processor-SoC
inferred← citeshttps://doi.org/10.1145/2544350.2544354openalex-snapshot
Multi-core composability in the face of memory-bus contention
inferred← citeshttps://doi.org/10.1145/2834848.2834854openalex-snapshot
Memory-processor co-scheduling in fixed priority systems
inferred← citeshttps://doi.org/10.1145/3178442.3178444openalex-snapshot
Combining PREM compilation and ILP scheduling for high-performance and predictable MPSoC execution
inferred← citeshttps://doi.org/10.1145/3323212openalex-snapshot
A Survey of Timing Verification Techniques for Multi-Core Real-Time Systems
inferred← citeshttps://doi.org/10.1145/3465370openalex-snapshot
The Predictable Execution Model in Practice
inferred← citeshttps://doi.org/10.1145/3548773openalex-snapshot
Evaluating Controlled Memory Request Injection for Efficient Bandwidth Utilization and Predictable Execution in Heterogeneous SoCs
inferred← citeshttps://doi.org/10.1145/3770858openalex-snapshot
Near-Optimal Cache Sharing through Co-Located Parallel Scheduling of Threads
inferred← citeshttps://doi.org/10.17706/jcp.14.8.507-518openalex-snapshot
An Effective Technique to Higher Throughput for Streaming Applications on an MPSoC
inferred← citeshttps://doi.org/10.17863/cam.62826openalex-snapshot
A SIMD architecture for hard real-time systems
inferred← citeshttps://doi.org/10.23919/date54114.2022.9774670openalex-snapshot
Cache-aware Schedulability Analysis of PREM Compliant Tasks
inferred← citeshttps://doi.org/10.48550/arxiv.1805.12041openalex-snapshot
BUNDLEP: Prioritizing Conflict Free Regions in Multi-Threaded Programs to Improve Cache Reuse -- Extended Results and Technical Report
inferred← citeshttps://doi.org/10.5120/17040-7350openalex-snapshot
An Effective Resource Partitioning Heuristic for Embedded Applications on an MPSoC
inferred← citeshttps://doi.org/10.70675/47acb842z2576z45e6z8bfczdf80d0226e97openalex-snapshot
Response time analysis of parameterized dataflow applications on heterogeneous SW/HW systems
inferred← citeshttps://doi.org/10.70675/d6347789zb698z4c81zbd5czb1f74a612a50openalex-snapshot
Caractérisation de la sensibilité aux interférences mémoire dans les systèmes temps-réels embarqués sur des plateformes multi-coeurs
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