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Instruction Cache Locking for Real-Time Embedded Systems with Multi-tasks

https://doi.org/10.1109/rtcsa.2009.59

0 signed · 16 inferred · view as graph

Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.

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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1023/a:1008145215849openalex-snapshot

Timing Analysis for Instruction Caches

inferredcites →https://doi.org/10.1109/ccece.2003.1226134openalex-snapshot

Static use of locking caches vs. dynamic use of locking caches for real-time systems

inferredcites →https://doi.org/10.1109/real.2002.1181567openalex-snapshot

Low-complexity algorithms for static cache locking in multitasking hard real-time systems

inferredcites →https://doi.org/10.1109/rtas.2009.11openalex-snapshot

Minimizing WCET for Real-Time Embedded Systems via Static Instruction Cache Locking

inferredcites →https://doi.org/10.1145/1289816.1289853openalex-snapshot

Compile-time decided instruction cache locking using worst-case execution paths

inferredcites →https://doi.org/10.3182/20020721-6-es-1901.00974openalex-snapshot

DYNAMIC USE OF LOCKING CACHES IN MULTITASK, PREEMPTIVE REAL-TIME SYSTEMS

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/s11227-019-02891-wopenalex-snapshot

Time-sensitivity-aware shared cache architecture for multi-core embedded systems

inferred← citeshttps://doi.org/10.1007/s11241-011-9139-4openalex-snapshot

Instruction cache locking for multi-task real-time embedded systems

inferred← citeshttps://doi.org/10.1016/j.jpdc.2011.05.006openalex-snapshot

Joint task assignment and cache partitioning with cache locking for WCET minimization on MPSoC

inferred← citeshttps://doi.org/10.1109/iccd.2013.6657097openalex-snapshot

Performance-controllable shared cache architecture for multi-core soft real-time systems

inferred← citeshttps://doi.org/10.1109/icpp.2010.65openalex-snapshot

Task Assignment with Cache Partitioning and Locking for WCET Minimization on MPSoC

inferred← citeshttps://doi.org/10.1109/rtas48715.2020.00006openalex-snapshot

The Potential of Programmable Logic in the Middle: Cache Bleaching

inferred← citeshttps://doi.org/10.1145/2680539openalex-snapshot

Joint WCET and Update Activity Minimization for Cyber-Physical Systems

inferred← citeshttps://doi.org/10.1145/2700100openalex-snapshot

Instruction-Cache Locking for Improving Embedded Systems Performance

inferred← citeshttps://doi.org/10.1145/2830555openalex-snapshot

A Survey on Cache Management Mechanisms for Real-Time Embedded Systems

inferred← citeshttps://doi.org/10.1145/2858792openalex-snapshot

A Survey of Techniques for Cache Locking

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