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A Survey of Techniques for Cache Locking

https://doi.org/10.1145/2858792
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1002/bltj.21532openalex-snapshot
Functional-Level Energy Characterization of µC/OS-II and Cache Locking for Energy Saving
inferredcites →https://doi.org/10.1007/s11241-012-9160-2openalex-snapshot
Timing analysis of concurrent programs running on shared cache multi-cores
inferredcites →https://doi.org/10.1007/s11265-011-0650-6openalex-snapshot
Instruction Cache Locking for Embedded Systems using Probability Profile
inferredcites →https://doi.org/10.1016/j.suscom.2013.11.001openalex-snapshot
A survey of architectural techniques for improving cache power efficiency
inferredcites →https://doi.org/10.1016/j.sysarc.2010.02.002openalex-snapshot
Improving cache locking performance of modern embedded systems via the addition of a miss table at the L2 cache level
inferredcites →https://doi.org/10.1023/a:1008138407139openalex-snapshot
An Integrated Path and Timing Analysis Method based on Cycle-Level Symbolic Execution
inferredcites →https://doi.org/10.1023/a:1008141130870openalex-snapshot
Fast and Precise WCET Prediction by Separated Cache and Path Analyses
inferredcites →https://doi.org/10.1109/aiccsa.2009.5069404openalex-snapshot
Impact of L1 entire locking and L2 way locking on the performance, power consumption, and predictability of multicore real-time systems
inferredcites →https://doi.org/10.1109/aiccsa16877.2010openalex-snapshot
ACS/IEEE International Conference on Computer Systems and Applications - AICCSA 2010
inferredcites →https://doi.org/10.1109/anthology.2013.6784761openalex-snapshot
Cache locking optimization in java virtual machine
inferredcites →https://doi.org/10.1109/ccece.2003.1226134openalex-snapshot
Static use of locking caches vs. dynamic use of locking caches for real-time systems
inferredcites →https://doi.org/10.1109/date.2007.364510openalex-snapshot
Scratchpad memories vs locked caches in hard real-time systems: a quantitative comparison
inferredcites →https://doi.org/10.1109/ecrts.2005.34openalex-snapshot
Cache Contents Selection for Statically-Locked Instruction Caches: An Algorithm Comparison
inferredcites →https://doi.org/10.1109/ecrts.2006.32openalex-snapshot
WCET-Centric Software-controlled Instruction Caches for Hard Real-Time Systems
inferredcites →https://doi.org/10.1109/ecrts.2012.27openalex-snapshot
Semi-Partitioned Hard-Real-Time Scheduling under Locked Cache Migration in Multicore Systems
inferredcites →https://doi.org/10.1109/ecrts.2013.26openalex-snapshot
Outstanding Paper Award: Making Shared Caches More Predictable on Multicore Platforms
inferredcites →https://doi.org/10.1109/iccd.2014.6974730openalex-snapshot
Cache design for mixed criticality real-time systems
inferredcites →https://doi.org/10.1109/icpp.2010.65openalex-snapshot
Task Assignment with Cache Partitioning and Locking for WCET Minimization on MPSoC
inferredcites →https://doi.org/10.1109/isorcw.2015.58openalex-snapshot
A Time-Predictable Instruction-Cache Architecture that Uses Prefetching and Cache Locking
inferredcites →https://doi.org/10.1109/real.1996.563722openalex-snapshot
Cache modeling for real-time software: beyond direct mapped instruction caches
inferredcites →https://doi.org/10.1109/real.1999.818824openalex-snapshot
Timing anomalies in dynamically scheduled microprocessors
inferredcites →https://doi.org/10.1109/real.2002.1181567openalex-snapshot
Low-complexity algorithms for static cache locking in multitasking hard real-time systems
inferredcites →https://doi.org/10.1109/rtas.2009.11openalex-snapshot
Minimizing WCET for Real-Time Embedded Systems via Static Instruction Cache Locking
inferredcites →https://doi.org/10.1109/rtcsa.2009.59openalex-snapshot
Instruction Cache Locking for Real-Time Embedded Systems with Multi-tasks
inferredcites →https://doi.org/10.1109/rtcsa.2010.8openalex-snapshot
Combining Prefetch with Instruction Cache Locking in Multitasking Real-Time Systems
inferredcites →https://doi.org/10.1109/secon.2015.7133036openalex-snapshot
Impact of L2 cache locking on GPU performance
inferredcites →https://doi.org/10.1109/secon.2015.7133037openalex-snapshot
Exploring hybrid cache locking to balance performance and time predictability
inferredcites →https://doi.org/10.1109/tcad.2009.2013287openalex-snapshot
Memory Hierarchies, Pipelines, and Buses for Future Architectures in Time-Critical Embedded Systems
inferredcites →https://doi.org/10.1109/tpds.2014.2324563openalex-snapshot
A Survey Of Architectural Approaches for Managing Embedded DRAM and Non-Volatile On-Chip Caches
inferredcites →https://doi.org/10.1109/vlsi-soc.2013.6673263openalex-snapshot
Data re-allocation enabled cache locking for embedded systems
inferredcites →https://doi.org/10.1142/s0218126614300025openalex-snapshot
A SURVEY OF TECHNIQUES FOR MANAGING AND LEVERAGING CACHES IN GPUs
inferredcites →https://doi.org/10.1145/1289816.1289853openalex-snapshot
Compile-time decided instruction cache locking using worst-case execution paths
inferredcites →https://doi.org/10.1145/1324969.1324973openalex-snapshot
Data cache locking for tight timing calculations
inferredcites →https://doi.org/10.1145/1391469.1391545openalex-snapshot
Exploring locking & partitioning for predictable shared caches on multi-cores
inferredcites →https://doi.org/10.1145/1629395.1629422openalex-snapshot
Instruction cache locking inside a binary rewriter
inferredcites →https://doi.org/10.1145/1837274.1837362openalex-snapshot
Instruction cache locking using temporal reuse profile
inferredcites →https://doi.org/10.1145/216633.216666openalex-snapshot
Performance analysis of embedded software using implicit path enumeration
inferredcites →https://doi.org/10.1145/217474.217570openalex-snapshot
Performance analysis of embedded software using implicit path enumeration
inferredcites →https://doi.org/10.1145/2228360.2228434openalex-snapshot
WCET-centric partial instruction cache locking
inferredcites →https://doi.org/10.1145/2259016.2259023openalex-snapshot
WCET-aware static locking of instruction caches
inferredcites →https://doi.org/10.1145/2463209.2488916openalex-snapshot
Integrated instruction cache analysis and locking in multitasking real-time systems
inferredcites →https://doi.org/10.1145/2597809.2597820openalex-snapshot
WCET
inferredcites →https://doi.org/10.1145/2638557openalex-snapshot
Static Task Partitioning for Locked Caches in Multicore Real-Time Systems
inferredcites →https://doi.org/10.1145/2660492openalex-snapshot
Branch Prediction-Directed Dynamic Instruction Cache Locking for Embedded Systems
inferredcites →https://doi.org/10.1145/2670529.2754965openalex-snapshot
WCET-Aware Dynamic D-cache Locking for A Single Task
inferredcites →https://doi.org/10.1145/2742060.2742076openalex-snapshot
Phase-based Cache Locking for Embedded Systems
inferredcites →https://doi.org/10.1145/781027.781062openalex-snapshot
Data cache locking for higher program predictability
inferredcites →https://doi.org/10.1145/885651.781062openalex-snapshot
Data cache locking for higher program predictability
inferredcites →https://doi.org/10.1371/journal.pone.0082975openalex-snapshot
Combining Instruction Prefetching with Partial Cache Locking to Improve WCET in Real-Time Systems
inferredcites →https://doi.org/10.1504/ijcaet.2014.065419openalex-snapshot
A survey of techniques for improving energy efficiency in embedded computing systems
inferredcites →https://doi.org/10.1504/ijcaet.2016.079392openalex-snapshot
A survey of power management techniques for phase change memory
inferredcites →https://doi.org/10.3182/20020721-6-es-1901.00974openalex-snapshot
DYNAMIC USE OF LOCKING CACHES IN MULTITASK, PREEMPTIVE REAL-TIME SYSTEMS
inferredcites →https://doi.org/10.7873/date2014.040openalex-snapshot
WCET-Centric dynamic instruction cache locking

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/978-3-319-62105-0_14openalex-snapshot
A Systematic Study of Cache Side Channels Across AES Implementations
inferred← citeshttps://doi.org/10.1007/s10009-018-0497-2openalex-snapshot
Scalable and precise estimation and debugging of the worst-case execution time for analysis-friendly processors: a comeback of model checking
inferred← citeshttps://doi.org/10.1007/s10586-017-1369-3openalex-snapshot
WCET optimization strategy based on source code refactoring
inferred← citeshttps://doi.org/10.1016/j.parco.2023.103023openalex-snapshot
A survey of software techniques to emulate heterogeneous memory systems in high-performance computing
inferred← citeshttps://doi.org/10.1016/j.sysarc.2021.102163openalex-snapshot
A survey on hardware security of DNN models and accelerators
inferred← citeshttps://doi.org/10.1016/j.sysarc.2026.103808openalex-snapshot
Shared caches for mixed-criticality 5G radio base station
inferred← citeshttps://doi.org/10.1088/1742-6596/1927/1/012003openalex-snapshot
A Smart Cache Lockdown Technique for IoT System
inferred← citeshttps://doi.org/10.1109/access.2022.3151891openalex-snapshot
A Survey of Techniques for Reducing Interference in Real-Time Applications on Multicore Platforms
inferred← citeshttps://doi.org/10.1109/access.2022.3230068openalex-snapshot
Improving the Configuration of the Predictable ACDC Data Cache for Real-Time Systems
inferred← citeshttps://doi.org/10.1109/etfa.2019.8869168openalex-snapshot
Combining watchdog processor with instruction cache locking for a fault-tolerant, predictable architecture applied to fixed-priority, preemptive, multitasking real-time systems
inferred← citeshttps://doi.org/10.1109/iccd.2016.7753310openalex-snapshot
“Stubborn” strategy to mitigate remaining cache misses
inferred← citeshttps://doi.org/10.1109/isca52012.2021.00027openalex-snapshot
ABC-DIMM: Alleviating the Bottleneck of Communication in DIMM-based Near-Memory Processing with Inter-DIMM Broadcast
inferred← citeshttps://doi.org/10.1109/isorc65339.2025.00034openalex-snapshot
Simulating Contention and Timeout Caches for a Mixed-Criticality 5G Radio Base Station
inferred← citeshttps://doi.org/10.1109/rtas54340.2022.00015openalex-snapshot
SBIs: Application Access to Safe, Baremetal Interrupt Latencies
inferred← citeshttps://doi.org/10.1109/rtas65571.2025.00015openalex-snapshot
Work in Progress: Optimizing Schedulability Using Cache-Bypassing
inferred← citeshttps://doi.org/10.1109/rtas65571.2025.00032openalex-snapshot
Arm Dynamiq Shared Unit and Real-Time: An Empirical Evaluation
inferred← citeshttps://doi.org/10.1109/rtcsa62462.2024.00021openalex-snapshot
Duration-based Instruction Cache Locking
inferred← citeshttps://doi.org/10.1109/tc.2025.3590809openalex-snapshot
PRECIOUS: Approximate Real-Time Computing in MLC-MRAM Based Heterogeneous CMPs
inferred← citeshttps://doi.org/10.1109/tcad.2018.2858459openalex-snapshot
Hot-Spot Suppression for Resource-Constrained Image Recognition Devices With Nonvolatile Memory
inferred← citeshttps://doi.org/10.1109/tcad.2024.3384442openalex-snapshot
ARCTIC: Approximate Real-Time Computing in a Cache-Conscious Multicore Environment
inferred← citeshttps://doi.org/10.1109/tvlsi.2017.2757477openalex-snapshot
PhLock: A Cache Energy Saving Technique Using Phase-Based Cache Locking
inferred← citeshttps://doi.org/10.1145/3126908.3126931openalex-snapshot
Exploring and analyzing the real impact of modern on-package memory on HPC scientific kernels
inferred← citeshttps://doi.org/10.1145/3306491openalex-snapshot
Formal Modeling and Verification of a Victim DRAM Cache
inferred← citeshttps://doi.org/10.1145/3358196openalex-snapshot
Cache Locking Content Selection Algorithms for ARINC-653 Compliant RTOS
inferred← citeshttps://doi.org/10.1145/3358224openalex-snapshot
MxU
inferred← citeshttps://doi.org/10.1145/3676641.3716014openalex-snapshot
Practical Federated Recommendation Model Learning Using ORAM with Controlled Privacy
inferred← citeshttps://doi.org/10.1371/journal.pone.0229980openalex-snapshot
Reducing the WCET and analysis time of systems with simple lockable instruction caches
inferred← citeshttps://doi.org/10.22360/springsim.2020.hpc.002openalex-snapshot
Simulator-based Framework towards Improved Cache Predictability for Multi-core Avionic System
inferred← citeshttps://doi.org/10.3390/app10072464openalex-snapshot
Execution Model to Reduce the Interference of Shared Memory in ARINC 653 Compliant Multicore RTOS
inferred← citeshttps://doi.org/10.3390/jlpea6020005openalex-snapshot
A Survey of Cache Bypassing Techniques
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