On the public citation graph

Combining Prefetch with Instruction Cache Locking in Multitasking Real-Time Systems

https://doi.org/10.1109/rtcsa.2010.8
0 signed · 36 inferred · view as graph

Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.

Is this your work? Sign in with ORCID and put your name on the claims that are yours.
Claim with ORCID
Reference health. See whether every reference in this work resolves to a known work and none has been retracted — and get a dated CiteStamped badge you can embed.
See reference health

What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1016/s1574-6526(06)x8001-xopenalex-snapshot
Handbook of Constraint Programming
inferredcites →https://doi.org/10.1023/a:1008138407139openalex-snapshot
An Integrated Path and Timing Analysis Method based on Cycle-Level Symbolic Execution
inferredcites →https://doi.org/10.1023/a:1008141130870openalex-snapshot
Fast and Precise WCET Prediction by Separated Cache and Path Analyses
inferredcites →https://doi.org/10.1023/a:1008145215849openalex-snapshot
Timing Analysis for Instruction Caches
inferredcites →https://doi.org/10.1023/b:time.0000045315.61234.1eopenalex-snapshot
Real Time Scheduling Theory: A Historical Perspective
inferredcites →https://doi.org/10.1109/12.677221openalex-snapshot
A performance study of instruction cache prefetching methods
inferredcites →https://doi.org/10.1109/32.950317openalex-snapshot
Bounding cache-related preemption delay for real-time systems
inferredcites →https://doi.org/10.1109/c-m.1978.218016openalex-snapshot
Sequential Program Prefetching in Memory Hierarchies
inferredcites →https://doi.org/10.1109/ccece.2003.1226134openalex-snapshot
Static use of locking caches vs. dynamic use of locking caches for real-time systems
inferredcites →https://doi.org/10.1109/ecrts.2005.26openalex-snapshot
Scheduling Analysis of Real-Time Systems with Precise Modeling of Cache Related Preemption Delay
inferredcites →https://doi.org/10.1109/ecrts.2006.32openalex-snapshot
WCET-Centric Software-controlled Instruction Caches for Hard Real-Time Systems
inferredcites →https://doi.org/10.1109/hpc.1997.592238openalex-snapshot
An improved lookahead instruction prefetching
inferredcites →https://doi.org/10.1109/micro.1999.809439openalex-snapshot
Fetch directed instruction prefetching
inferredcites →https://doi.org/10.1109/real.1996.563722openalex-snapshot
Cache modeling for real-time software: beyond direct mapped instruction caches
inferredcites →https://doi.org/10.1109/real.2002.1181567openalex-snapshot
Low-complexity algorithms for static cache locking in multitasking hard real-time systems
inferredcites →https://doi.org/10.1109/rtcsa.2008.10openalex-snapshot
Avoiding the WCET Overestimation on LRU Instruction Cache
inferredcites →https://doi.org/10.1109/rttas.1996.509537openalex-snapshot
Adding instruction cache effect to schedulability analysis of preemptive real-time systems
inferredcites →https://doi.org/10.1145/1324969.1324973openalex-snapshot
Data cache locking for tight timing calculations
inferredcites →https://doi.org/10.3182/20020721-6-es-1901.00974openalex-snapshot
DYNAMIC USE OF LOCKING CACHES IN MULTITASK, PREEMPTIVE REAL-TIME SYSTEMS
inferredcites →https://doi.org/10.5555/290940.290979openalex-snapshot
Cooperative prefetching: compiler and hardware support for effective instruction prefetching in modern processors
inferredcites →https://doi.org/10.5555/320080.320085openalex-snapshot
Fetch directed instruction prefetching

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1016/j.sysarc.2013.07.012openalex-snapshot
Optimizing a combined WCET-WCEC problem in instruction fetching for real-time systems
inferred← citeshttps://doi.org/10.1016/j.sysarc.2015.05.001openalex-snapshot
A predictable hardware to exploit temporal reuse in real-time and embedded systems
inferred← citeshttps://doi.org/10.1016/j.sysarc.2021.102304openalex-snapshot
A generic framework to integrate data caches in the WCET analysis of real-time systems
inferred← citeshttps://doi.org/10.1109/access.2022.3230068openalex-snapshot
Improving the Configuration of the Predictable ACDC Data Cache for Real-Time Systems
inferred← citeshttps://doi.org/10.1109/icce-asia.2016.7804786openalex-snapshot
Enhanced rolling cache architecture with prefetch
inferred← citeshttps://doi.org/10.1109/icsess.2013.6615334openalex-snapshot
Texture transmission optimization and prefetching in GPU hard accelerated rendering
inferred← citeshttps://doi.org/10.1109/isorcw.2011.41openalex-snapshot
Using a Local Prefetch Strategy to Obtain Temporal Time Predictability
inferred← citeshttps://doi.org/10.1109/isorcw.2015.58openalex-snapshot
A Time-Predictable Instruction-Cache Architecture that Uses Prefetching and Cache Locking
inferred← citeshttps://doi.org/10.1109/rtas.2012.11openalex-snapshot
A Small and Effective Data Cache for Real-Time Multitasking Systems
inferred← citeshttps://doi.org/10.1145/2463209.2488915openalex-snapshot
Reconciling real-time guarantees and energy efficiency through unlocked-cache prefetching
inferred← citeshttps://doi.org/10.1145/2677093openalex-snapshot
ACDC
inferred← citeshttps://doi.org/10.1145/2858792openalex-snapshot
A Survey of Techniques for Cache Locking
inferred← citeshttps://doi.org/10.1371/journal.pone.0082975openalex-snapshot
Combining Instruction Prefetching with Partial Cache Locking to Improve WCET in Real-Time Systems
inferred← citeshttps://doi.org/10.1371/journal.pone.0229980openalex-snapshot
Reducing the WCET and analysis time of systems with simple lockable instruction caches
inferred← citeshttps://doi.org/10.5821/dissertation-2117-366909openalex-snapshot
Smart hardware designs for probabilistically-analyzable processor architectures
Editorial review for independent work. ICSAC — the Institute for Complexity Science and Advanced Computing — runs a structured editorial panel for researchers publishing outside journals, and publishes on CiteStamp rails. Submission is free and goes through ORCID: icsacinstitute.org/submit.