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Silencing Hardware Backdoors
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1109/hst.2008.4559038openalex-snapshot
At-speed delay characterization for IC authentication and Trojan Horse detection
inferredcites →https://doi.org/10.1109/hst.2008.4559039openalex-snapshot
Detecting malicious inclusions in secure hardware: Challenges and solutions
inferredcites →https://doi.org/10.1109/hst.2008.4559047openalex-snapshot
A region based approach for the identification of hardware Trojans
inferredcites →https://doi.org/10.1109/hst.2008.4559048openalex-snapshot
On-demand transparency for improving hardware Trojan detectability
inferredcites →https://doi.org/10.1109/hst.2008.4559049openalex-snapshot
Hardware Trojan detection using path delay fingerprint
inferredcites →https://doi.org/10.1109/hst.2009.5224968openalex-snapshot
New design strategy for improving hardware Trojan detection and reducing Trojan activation time
inferredcites →https://doi.org/10.1109/iccad.2008.4681643openalex-snapshot
Power supply signal calibration techniques for improving detection resolution to hardware Trojans
inferredcites →https://doi.org/10.1109/ispass.2009.4919638openalex-snapshot
Zesto: A cycle-level simulator for highly detailed microarchitecture exploration
inferredcites →https://doi.org/10.1109/mdt.2010.25openalex-snapshot
Secure and robust error correction for physical unclonable functions
inferredcites →https://doi.org/10.1109/mspec.2008.4505310openalex-snapshot
The Hunt For The Kill Switch
inferredcites →https://doi.org/10.1109/sp.2007.36openalex-snapshot
Trojan Detection using IC Fingerprinting
inferredcites →https://doi.org/10.1109/sp.2010.18openalex-snapshot
Overcoming an Untrusted Computing Base: Detecting and Removing Malicious Hardware Automatically
inferredcites →https://doi.org/10.1109/sp.2010.39openalex-snapshot
SCiFI - A System for Secure Face Identification
inferredcites →https://doi.org/10.1109/vlsic.2004.1346548openalex-snapshot
A technique to build a secret key in integrated circuits for identification and authentication applications
inferredcites →https://doi.org/10.1145/1047915.1047919openalex-snapshot
Improving the reliability of commodity operating systems
inferredcites →https://doi.org/10.1145/1278480.1278484openalex-snapshot
Physical unclonable functions for device authentication and secret key generation
inferredcites →https://doi.org/10.1145/1366110.1366196openalex-snapshot
Guided test generation for isolation and detection of embedded trojans in ics
inferredcites →https://doi.org/10.1145/1666420.1666444openalex-snapshot
Computing arbitrary functions of encrypted data
inferredcites →https://doi.org/10.1145/586110.586132openalex-snapshot
Silicon physical random functions
inferredcites →https://doi.org/10.1145/945445.945466openalex-snapshot
Improving the reliability of commodity operating systems
inferredcites →https://doi.org/10.5555/1509456.1509596openalex-snapshot
Power supply signal calibration techniques for improving detection resolution to hardware Trojans
inferredcites →https://doi.org/10.6028/nist.ir.7622openalex-snapshot
Notional Supply Chain Risk Management Practices for Federal Information Systems
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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Hardware Trojan detection for lightweight ciphers implemented on field‐programmable gate arrays using the replay algorithm
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Secure Outsourcing of Cryptographic Circuits Manufacturing
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Hardware Trojans in Microcircuits
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Methods of Detecting Hardware Trojans in Microcircuits
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Countermeasures Against Hardware Trojans
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Hardware Trojan Localization: Modeling and Empirical Approach
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Reconstructing and Visualizing Evidence of Artifact from Firefox SessionStorage
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Verification and Trust for Unspecified IP Functionality
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Validation of IP Security and Trust
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Security Assurance in SoC in the Presence of Untrusted Components
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A Survey of Research on Smart Grid Security
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Preventing Backdoors in Server Applications with a Separated Software Architecture
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Stealthy Dopant-Level Hardware Trojans
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A Design Methodology for Stealthy Parametric Trojans and Its Application to Bug Attacks
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Subverting Cryptographic Protocols from a Fine-Grained Perspective- A Case Study on 2-Party ECDSA
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Two Countermeasures Against Hardware Trojans Exploiting Non-Zero Aliasing Probability of BIST
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Trusted Integrated Circuits: The Problem and Challenges
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A stealthy Hardware Trojan based on a Statistical Fault Attack
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Stealthy dopant-level hardware Trojans: extended version
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Trust Filter: Runtime Hardware Trojan Detection in Behavioral MPSoCs
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Surveying the Hardware Trojan Threat Landscape for the Internet-of-Things
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Targeted modification of hardware trojans
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A survey on physical unclonable function (PUF)-based security solutions for Internet of Things
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A problem shared is a problem halved: A survey on the dimensions of collective cyber defense through security information sharing
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Symbolic execution based test-patterns generation algorithm for hardware Trojan detection
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System-level protection and hardware Trojan detection using weighted voting
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TASPDetect: Reviving Trust in 3PIP By Detecting TASP Trojans
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VLSI supply chain security risks and mitigation techniques: A survey
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Online detection of hardware Trojan enabled packet tampering attack on network-on-chip: A Bayesian approach
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A problem shared is a problem halved
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A Review on HT Attacks in PLD and ASIC Designs with Potential Defence Solutions
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Consumer electronics supply chain poisoning: anatomizing the unified hardware and software threat model and countermeasures
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Mobile Social Networking Under Side-Channel Attacks: Practical Security Challenges
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Ingress of Threshold Voltage-Triggered Hardware Trojan in the Modern FPGA Fabric–Detection Methodology and Mitigation
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On the Security of Symmetric Encryption Against Mass Surveillance
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Ransomware Attack as Hardware Trojan: A Feasibility and Demonstration Study
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DoSGuard: Protecting pipelined MPSoCs against hardware Trojan based DoS attacks
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Acquisition of Evidence of Web Storage in HTML5 Web Browsers from Memory Image
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PCH framework for IP runtime security verification
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Hardware Trojan detection using exhaustive testing of k-bit subspaces
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Detecting hardware Trojans in unspecified functionality through solving satisfiability problems
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Secure Federated Learning for Gate-Level IP Hardware Trojan Detection Using Homomorphic Encryption
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Detecting and thwarting hardware trojan attacks in cyber-physical systems
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Exploring the Limitations of the Property-based Hardware-Trojan Detection Methods
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Self-Guarding Cryptographic Protocols against Algorithm Substitution Attacks
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A red team/blue team assessment of functional analysis methods for malicious circuit identification
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SAFER PATH: Security architecture using fragmented execution and replication for protection against trojaned hardware
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Computing with obfuscated data in arbitrary logic circuits via noise insertion and cancellation
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Shielding heterogeneous MPSoCs from untrustworthy 3PIPs through security-driven task scheduling
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Hardware Trojan Protection for Third Party IPs
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Run-time detection of hardware Trojans: The processor protection unit
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Evaluating security requirements in a general-purpose processor by combining assertion checkers with code coverage
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FPGA SoC architecture and runtime to prevent hardware Trojans from leaking secrets
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Hardware security: Threat models and metrics
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Block-Chain-Based Personal Data Hosting
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Automatic Hardware Trojan Generation Platforms in Integrated Circuits: A Critical Review
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High-level synthesis for security and trust
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Deep Learning Based Approach for Hardware Trojan Detection
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A Primer on Hardware Security: Models, Methods, and Metrics
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Jintide: Utilizing Low-Cost Reconfigurable External Monitors to Substantially Enhance Hardware Security of Large-Scale CPU Clusters
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Do Not Trust, Verify: A Verifiable Hardware Accelerator for Matrix Multiplication
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Practical, Lightweight Secure Inclusion of Third-Party Intellectual Property
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FinalFilter: Asserting Security Properties of a Processor at Runtime
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Hardware Trojan detection in soft error tolerant macro synchronous micro asynchronous (MSMA) pipeline
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Exploring Graph Neural Backdoors in Vehicular Networks: Fundamentals, Methodologies, Applications, and Future Perspectives
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Hardware Trojan detection methodology for FPGA
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Smart employment of circuit redundancy to effectively counter trojans (SECRET) in third-party IP cores
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Defeating hardware spyware in third party IPs
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A Framework to Eliminate Backdoors from Response-Computable Authentication
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Bomberman: Defining and Defeating Hardware Ticking Timebombs at Design-time
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Toward a Trustable, Self-Hosting Computer System
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Trojan Detection in Embedded Systems With FinFET Technology
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VeriTrust: Verification for Hardware Trust
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TPAD: Hardware Trojan Prevention and Detection for Trusted Integrated Circuits
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Hiding Hardware Trojan Communication Channels in Partially Specified SoC Bus Functionality
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DRMaSV: Enhanced Capability Against Hardware Trojans in Coarse Grained Reconfigurable Architectures
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Secure Randomized Checkpointing for Digital Microfluidic Biochips
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Hardware Trojan Detection Using Backside Optical Imaging
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GNN-RE: Graph Neural Networks for Reverse Engineering of Gate-Level Netlists
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Applying Chaos Theory for Runtime Hardware Trojan Monitoring and Detection
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Trojan Detection in Digital Microfluidic Biochips via Image Classification: A Deep-Learning Based Approach
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Hardware Trojans hidden in RTL don't cares — Automated insertion and prevention methodologies
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Securing digital microfluidic biochips by randomizing checkpoints
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Reverse Engineering Digital Circuits Using Structural and Functional Analyses
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Shielding Heterogeneous MPSoCs From Untrustworthy 3PIPs Through Security- Driven Task Scheduling
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Securing Cyber-Physical Systems from Hardware Trojan Collusion
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Security Assurance for System-on-Chip Designs With Untrusted IPs
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Security Implications of Intentional Capacitive Crosstalk
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Designing Energy-Efficient MPSoC with Untrustworthy 3PIP Cores
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Fingerprint-Based Detection and Diagnosis of Malicious Programs in Hardware
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Architectural refinements for enhancing trust and securing cyber-physical systems
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E-Voting Attacks and Countermeasures
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Wireless security techniques for coordinated manufacturing and on-line hardware trojan detection
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Towards reducing the attack surface of software backdoors
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Exploiting heterogeneity in MPSoCs to prevent potential trojan propagation across malicious IPs
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A Red Team/Blue Team Assessment of Functional Analysis Methods for Malicious Circuit Identification
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Trustworthy hardware from untrusted components
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Detecting malicious modifications of data in third-party intellectual property cores
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Real-Time Anomaly Detection Framework for Many-Core Router through Machine-Learning Techniques
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Exploiting the analog properties of digital circuits for malicious hardware
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Efficient Control-Flow Subgraph Matching for Detecting Hardware Trojans in RTL Models
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Implementing Trojan-Resilient Hardware from (Mostly) Untrusted Components Designed by Colluding Manufacturers
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Architectural Support for Containment-based Security
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Hardware Trojan Mitigation in Pipelined MPSoCs
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Eternal-thing 2.0: Analog-Trojan-resilient Ripple-less Solar Harvesting System for Sustainable IoT
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HLS-IRT: Hardware Trojan Insertion through Modification of Intermediate Representation During High-Level Synthesis
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Dynamic FPGA Detection and Protection of Hardware Trojan: A Comparative Analysis
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HaTCh: Hardware Trojan Catcher
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Trojan Counteraction in Hardware: A Survey and New Taxonomy
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HIT: A Hidden Instruction Trojan Model for Processors
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Overview of security problems and the design of secure electronic system
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FEINT: Automated Framework for Efficient INsertion of Templates/Trojans into FPGAs
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Dual-Metric Detection of Synthesis-Masked Hardware Trojans in AES-256: Correlating Power Signatures with Switching Activity
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Hardware Trojans in Incompletely Specified On-chip Bus Systems
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MOE: Multiplication Operated Encryption with Trojan Resilience
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Intellectual Property Design with PUF-based Hardware Security
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Dynamic FPGA Detection and Protection of Hardware Trojan: A Comparative Analysis
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Boosting the Bounds of Symbolic QED for Effective Pre-Silicon Verification of Processor Cores
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Security Assessment of Interposer-based Chiplet Integration
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SAFER PATH: security architecture using fragmented execution and replication for protection against trojaned hardware
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Mapping mixed-criticality applications on multi-core architectures
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Intentional and Unintentional Side-Channels in Embedded Systems
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Hacking and protecting IC hardware
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Cost and Scalability of Hardware Encryption Techniques
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Producing Trustworthy Hardware Using Untrusted Components, Personnel and Resources
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