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CAD-Base

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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/3-540-61474-5_93openalex-snapshot

Symbolic model checking

inferredcites →https://doi.org/10.1007/978-3-319-11824-6openalex-snapshot

Counterfeit Integrated Circuits: Detection and Avoidance

inferredcites →https://doi.org/10.1007/978-3-319-11824-6_2openalex-snapshot

Counterfeit Integrated Circuits

inferredcites →https://doi.org/10.1007/978-3-540-68914-0_8openalex-snapshot

Attacking Reduced Round SHA-256

inferredcites →https://doi.org/10.1007/978-3-642-04138-9_28openalex-snapshot

MERO: A Statistical Approach for Hardware Trojan Detection

inferredcites →https://doi.org/10.1007/978-3-642-38348-9_23openalex-snapshot

Improved Key Recovery Attacks on Reduced-Round AES in the Single-Key Setting

inferredcites →https://doi.org/10.1007/978-3-642-40349-1_12openalex-snapshot

Stealthy Dopant-Level Hardware Trojans

inferredcites →https://doi.org/10.1016/0141-9331(94)90007-8openalex-snapshot

Symbolic Model Checking

inferredcites →https://doi.org/10.1016/s0065-2458(03)58003-2openalex-snapshot

Bounded Model Checking

inferredcites →https://doi.org/10.1109/43.265680openalex-snapshot

An approach to the analysis and detection of crosstalk faults in digital VLSI circuits

inferredcites →https://doi.org/10.1109/acsac.2006.20openalex-snapshot

Covert and Side Channels Due to Processor Architecture

inferredcites →https://doi.org/10.1109/aspdac.2017.7858388openalex-snapshot

Trojan localization using symbolic algebra

inferredcites →https://doi.org/10.1109/ats.2012.61openalex-snapshot

TSV Stress-Aware ATPG for 3D Stacked ICs

inferredcites →https://doi.org/10.1109/date.2011.5763307openalex-snapshot

Multi-level attacks: An emerging security concern for cryptographic hardware

inferredcites →https://doi.org/10.1109/fpl.2013.6645550openalex-snapshot

Bambu: A modular framework for the high level synthesis of memory-intensive applications

inferredcites →https://doi.org/10.1109/hldvt.2009.5340158openalex-snapshot

Hardware Trojan: Threats and emerging solutions

inferredcites →https://doi.org/10.1109/hst.2008.4559038openalex-snapshot

At-speed delay characterization for IC authentication and Trojan Horse detection

inferredcites →https://doi.org/10.1109/hst.2008.4559052openalex-snapshot

Extended abstract: Circuit CAD tools as a security threat

inferredcites →https://doi.org/10.1109/hst.2009.5224959openalex-snapshot

OS support for detecting Trojan circuit attacks

inferredcites →https://doi.org/10.1109/hst.2011.5954998openalex-snapshot

Case study: Detecting hardware Trojans in third-party digital IP cores

inferredcites →https://doi.org/10.1109/iccd.2011.6081413openalex-snapshot

Sequential hardware Trojan: Side-channel aware design and placement

inferredcites →https://doi.org/10.1109/iiswc.2014.6983050openalex-snapshot

MachSuite: Benchmarks for accelerator design and customized architectures

inferredcites →https://doi.org/10.1109/isqed.2014.6783318openalex-snapshot

Efficient trace signal selection using augmentation and ILP techniques

inferredcites →https://doi.org/10.1109/jproc.2014.2334493openalex-snapshot

Hardware Trojan Attacks: Threat Analysis and Countermeasures

inferredcites →https://doi.org/10.1109/mc.2010.284openalex-snapshot

Ending Piracy of Integrated Circuits

inferredcites →https://doi.org/10.1109/mdat.2017.2735383openalex-snapshot

Challenges and Trends in Modern SoC Design Verification

inferredcites →https://doi.org/10.1109/mdat.2018.2824121openalex-snapshot

Enabling Automated Bug Detection for IP-Based Designs Using High-Level Synthesis

inferredcites →https://doi.org/10.1109/mdt.2004.1277905openalex-snapshot

A top-down methodology for microprocessor validation

inferredcites →https://doi.org/10.1109/mdt.2008.166openalex-snapshot

Managing Security in FPGA-Based Embedded Systems

inferredcites →https://doi.org/10.1109/mdt.2010.7openalex-snapshot

A Survey of Hardware Trojan Taxonomy and Detection

inferredcites →https://doi.org/10.1109/mse.2007.44openalex-snapshot

FreePDK: An Open-Source Variation-Aware Design Kit

inferredcites →https://doi.org/10.1109/sp.2007.36openalex-snapshot

Trojan Detection using IC Fingerprinting

inferredcites →https://doi.org/10.1109/sp.2010.18openalex-snapshot

Overcoming an Untrusted Computing Base: Detecting and Removing Malicious Hardware Automatically

inferredcites →https://doi.org/10.1109/sp.2011.27openalex-snapshot

Silencing Hardware Backdoors

inferredcites →https://doi.org/10.1109/sp.2011.32openalex-snapshot

Defeating UCI: Building Stealthy and Malicious Hardware

inferredcites →https://doi.org/10.1109/sp.2016.10openalex-snapshot

A2: Analog Malicious Hardware

inferredcites →https://doi.org/10.1109/tc.1972.5009015openalex-snapshot

On the Synthesis of Finite-State Machines from Samples of Their Behavior

inferredcites →https://doi.org/10.1109/tcad.2015.2513673openalex-snapshot

A Survey and Evaluation of FPGA High-Level Synthesis Tools

inferredcites →https://doi.org/10.1109/tcad.2016.2587278openalex-snapshot

A Unified Design Flow to Automatically Generate On-Chip Monitors during High-Level Synthesis of Hardware Accelerators

inferredcites →https://doi.org/10.1109/test.2003.1271098openalex-snapshot

A case study of ir-drop in structured at-speed testing

inferredcites →https://doi.org/10.1109/test.2011.6139157openalex-snapshot

Efficient combination of trace and scan signals for post silicon validation and debug

inferredcites →https://doi.org/10.1109/test.2015.7342387openalex-snapshot

Hardware Trojans hidden in RTL don't cares — Automated insertion and prevention methodologies

inferredcites →https://doi.org/10.1109/tvlsi.2012.2192457openalex-snapshot

RATS: Restoration-Aware Trace Signal Selection for Post-Silicon Validation

inferredcites →https://doi.org/10.1109/vlsid.2016.143openalex-snapshot

Formal Security Verification of Third Party Intellectual Property Cores for Information Leakage

inferredcites →https://doi.org/10.1145/1120725.1120856openalex-snapshot

Evaluation of the statistical delay quality model

inferredcites →https://doi.org/10.1145/1278480.1278547openalex-snapshot

CAD-based security, cryptography, and digital rights management

inferredcites →https://doi.org/10.1145/1687399.1687425openalex-snapshot

MOLES

inferredcites →https://doi.org/10.1145/1837274.1837435openalex-snapshot

Synthesis of trustable ICs using untrusted CAD tools

inferredcites →https://doi.org/10.1145/2508859.2516654openalex-snapshot

FANCI

inferredcites →https://doi.org/10.1145/2638555openalex-snapshot

Designing Trusted Embedded Systems from Finite State Machines

inferredcites →https://doi.org/10.1145/266021.266090openalex-snapshot

Equivalence checking using cuts and heaps

inferredcites →https://doi.org/10.1145/2744769.2744823openalex-snapshot

Detecting malicious modifications of data in third-party intellectual property cores

inferredcites →https://doi.org/10.1145/2897937.2897992openalex-snapshot

AVFSM

inferredcites →https://doi.org/10.1145/2976749.2978396openalex-snapshot

MERS

inferredcites →https://doi.org/10.1145/3126564openalex-snapshot

Using Efficient Path Profiling to Optimize Memory Consumption of On-Chip Debugging for High-Level Synthesis

inferredcites →https://doi.org/10.1145/800157.805047openalex-snapshot

The complexity of theorem-proving procedures

inferredcites →https://doi.org/10.2197/ipsjjip.17.242openalex-snapshot

Proposal and Quantitative Analysis of the CHStone Benchmark Program Suite for Practical C-based High-level Synthesis

inferredcites →https://doi.org/10.5555/2132325.2132461openalex-snapshot

Simulation-based signal selection for state restoration in silicon debug

inferredcites →https://doi.org/10.5555/285730.285734openalex-snapshot

VLSI design synthesis with testability

inferredcites →https://doi.org/10.5555/339492.340030openalex-snapshot

Fault modeling and simulation for crosstalk in system-on-chip interconnects

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/978-3-030-85792-9_1openalex-snapshot

Introduction

inferred← citeshttps://doi.org/10.1007/978-3-031-15030-2_3openalex-snapshot

Model Based Resilience Engineering for Design and Assessment of Mission Critical Systems Containing Artificial Intelligence Components

inferred← citeshttps://doi.org/10.1007/s10836-022-06035-6openalex-snapshot

A CatBoost Based Approach to Detect Label Flipping Poisoning Attack in Hardware Trojan Detection Systems

inferred← citeshttps://doi.org/10.1016/j.engappai.2024.109414openalex-snapshot

CADefender: Detection of unknown malicious AutoLISP computer-aided design files using designated feature extraction and machine learning methods

inferred← citeshttps://doi.org/10.1016/j.sysarc.2022.102543openalex-snapshot

Is your FPGA bitstream Hardware Trojan-free? Machine learning can provide an answer

inferred← citeshttps://doi.org/10.1016/j.sysarc.2023.103006openalex-snapshot

Secure Routing Framework for Mitigating Time-Delay Trojan Attack in System-on-Chip

inferred← citeshttps://doi.org/10.1049/iet-cdt.2020.0041openalex-snapshot

Ten years of hardware Trojans: a survey from the attacker's perspective

inferred← citeshttps://doi.org/10.1109/access.2020.2978815openalex-snapshot

Additive Manufacturing Cyber-Physical System: Supply Chain Cybersecurity and Risks

inferred← citeshttps://doi.org/10.1109/access.2020.2989735openalex-snapshot

Hardware Trojan Detection Using Controlled Circuit Aging

inferred← citeshttps://doi.org/10.1109/access.2022.3209705openalex-snapshot

Data Augmented Hardware Trojan Detection Using Label Spreading Algorithm Based Transductive Learning for Edge Computing-Assisted IoT Devices

inferred← citeshttps://doi.org/10.1109/access.2025.3555166openalex-snapshot

A Survey on the Design, Detection, and Prevention of Pre-Silicon Hardware Trojans

inferred← citeshttps://doi.org/10.1109/asp-dac66049.2026.11420824openalex-snapshot

Safeguarding Neural Network IPs from Scan Chain based Model Extraction Attacks

inferred← citeshttps://doi.org/10.1109/ats59501.2023.10318015openalex-snapshot

SMASh: A State Encoding Methodology Against Attacks on Finite State Machines

inferred← citeshttps://doi.org/10.1109/iccad51958.2021.9643543openalex-snapshot

Security Closure of Physical Layouts ICCAD Special Session Paper

inferred← citeshttps://doi.org/10.1109/iscas51556.2021.9401254openalex-snapshot

Design of Hardware Trojans and its Impact on CPS Systems: A Comprehensive Survey

inferred← citeshttps://doi.org/10.1109/iscas51556.2021.9401609openalex-snapshot

Can Overclocking Detect Hardware Trojans?

inferred← citeshttps://doi.org/10.1109/jetcas.2021.3084400openalex-snapshot

Two Sides of the Same Coin: Boons and Banes of Machine Learning in Hardware Security

inferred← citeshttps://doi.org/10.1109/jiot.2025.3528744openalex-snapshot

Advanced Persistent Threats Based on Supply Chain Vulnerabilities: Challenges, Solutions, and Future Directions

inferred← citeshttps://doi.org/10.1109/les.2023.3327793openalex-snapshot

Revisiting Black-Hat HLS: A Lightweight Countermeasure to HLS-Aided Trojan Attack

inferred← citeshttps://doi.org/10.1109/les.2023.3329417openalex-snapshot

Using Static Analysis for Enhancing HLS Security

inferred← citeshttps://doi.org/10.1109/mcsoc64144.2024.00044openalex-snapshot

Hardware Attack Models in Tiled Chip Multi-Core Processors: A Survey

inferred← citeshttps://doi.org/10.1109/mlcad65511.2025.11189143openalex-snapshot

HADA: Leveraging Multi-Source Data to Train Large Language Models for Hardware Security Assertion Generation

inferred← citeshttps://doi.org/10.1109/mwscas48704.2020.9184612openalex-snapshot

Challenges and New Directions for AI and Hardware Security

inferred← citeshttps://doi.org/10.1109/newcas57931.2023.10198066openalex-snapshot

Exploring Security Threats by Hardware-Faults in Approximate Arithmetic Computing

inferred← citeshttps://doi.org/10.1109/primeasia60757.2023.00019openalex-snapshot

Analyzing Area and Latency Overhead in C and RTL Locked Designs

inferred← citeshttps://doi.org/10.1109/tcad.2020.3012649openalex-snapshot

Exposing Hardware Trojans in Embedded Platforms via Short-Term Aging

inferred← citeshttps://doi.org/10.1109/tcad.2020.3024780openalex-snapshot

Training Data Poisoning in ML-CAD: Backdooring DL-Based Lithographic Hotspot Detectors

inferred← citeshttps://doi.org/10.1109/tcad.2020.3033749openalex-snapshot

Bias Busters: Robustifying DL-Based Lithographic Hotspot Detectors Against Backdooring Attacks

inferred← citeshttps://doi.org/10.1109/tcad.2021.3110807openalex-snapshot

GNN-RE: Graph Neural Networks for Reverse Engineering of Gate-Level Netlists

inferred← citeshttps://doi.org/10.1109/tcad.2022.3200513openalex-snapshot

BLAST: Belling the Black-Hat High-Level Synthesis Tool

inferred← citeshttps://doi.org/10.1109/tcad.2023.3234440openalex-snapshot

Circuit Topology-Aware Vaccination-Based Hardware Trojan Detection

inferred← citeshttps://doi.org/10.1109/tifs.2024.3372809openalex-snapshot

(Security) Assertions by Large Language Models

inferred← citeshttps://doi.org/10.1109/tr.2025.3547739openalex-snapshot

Insights From Bugs in FPGA High-Level Synthesis Tools: An Empirical Study of Bambu Bugs

inferred← citeshttps://doi.org/10.1109/vlsid60093.2024.00063openalex-snapshot

CAD Tools Pathway in Hardware Security

inferred← citeshttps://doi.org/10.1145/3372780.3378175openalex-snapshot

Hardware Security For and Beyond CMOS Technology

inferred← citeshttps://doi.org/10.1145/3386263.3407654openalex-snapshot

Trust Issues in COTS: The Challenges and Emerging Solution

inferred← citeshttps://doi.org/10.1145/3394885.3431571openalex-snapshot

Attacking a CNN-based Layout Hotspot Detector Using Group Gradient Method

inferred← citeshttps://doi.org/10.1145/3400302.3415684openalex-snapshot

A lightweight approach to detect malicious/unexpected changes in the error rates of NISQ computers

inferred← citeshttps://doi.org/10.1145/3408288openalex-snapshot

Adversarial Perturbation Attacks on ML-based CAD: A Case Study on CNN-based Lithographic Hotspot Detection

inferred← citeshttps://doi.org/10.1145/3439706.3446902openalex-snapshot

Hardware Security for and beyond CMOS Technology

inferred← citeshttps://doi.org/10.1145/3485832.3485911openalex-snapshot

LaserShark: Establishing Fast, Bidirectional Communication into Air-Gapped Systems

inferred← citeshttps://doi.org/10.1145/3494697openalex-snapshot

A Survey on Security of Digital Microfluidic Biochips: Technology, Attack, and Defense

inferred← citeshttps://doi.org/10.1145/3577200openalex-snapshot

High-Level Approaches to Hardware Security: A Tutorial

inferred← citeshttps://doi.org/10.1145/3663477openalex-snapshot

HLS-IRT: Hardware Trojan Insertion through Modification of Intermediate Representation During High-Level Synthesis

inferred← citeshttps://doi.org/10.1145/3716502openalex-snapshot

A New Dynamic Countermeasure to Strengthen Design Obfuscation in FPGAs

inferred← citeshttps://doi.org/10.1145/3795509openalex-snapshot

Detecting Hardware Trojans in High-Level Synthesis-Generated RTL using Large Language Models

inferred← citeshttps://doi.org/10.1145/3806057openalex-snapshot

GED-Net: A Multi-modal Reconstruction Network for CAD Parametric Models based on Grouped Entity Decoding

inferred← citeshttps://doi.org/10.1145/3822512openalex-snapshot

Efficient Error Detection for NTT Using Algebraic Invariants (AIC) Checking for PQC and FHE on FPGA

inferred← citeshttps://doi.org/10.23919/date48585.2020.9116489openalex-snapshot

Poisoning the (Data) Well in ML-Based CAD: A Case Study of Hiding Lithographic Hotspots

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