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Test and on-line debug capabilities of IEEE Std 1149.1 in UltraSPARC/sup TM/-III microprocessor

https://doi.org/10.1109/test.2000.894201

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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1109/isscc.1992.200409openalex-snapshot

A CMOS low-voltage-swing transmission-line transceiver

inferredcites →https://doi.org/10.1109/isscc.2000.839770openalex-snapshot

Dynamic termination output driver for a 600 MHz microprocessor

inferredcites →https://doi.org/10.1109/isscc.2000.839837openalex-snapshot

UltraSPARC-III: a 3rd generation 64 b SPARC microprocessor

inferredcites →https://doi.org/10.1109/isscc.2000.839838openalex-snapshot

Implementation of a 3rd-generation SPARC V9 64 b microprocessor

inferredcites →https://doi.org/10.1109/test.1995.529829openalex-snapshot

Testability, debuggability, and manufacturability features of the UltraSPARC-I microprocessor

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

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Design of Scan Cell for System on Chip Scan Based Debugging Applications

inferred← citeshttps://doi.org/10.1007/s10836-013-5426-4openalex-snapshot

Clock Faults Induced Min and Max Delay Violations

inferred← citeshttps://doi.org/10.1007/s11741-005-0068-0openalex-snapshot

Analyzing and seeking minimum test instruction set of digital signal processor for motor control

inferred← citeshttps://doi.org/10.1016/s0141-9331(02)00014-5openalex-snapshot

Linux-based experimental boundary scan environment

inferred← citeshttps://doi.org/10.1109/arftg.2001.327454openalex-snapshot

High-Throughput RFIC Wafer Testing

inferred← citeshttps://doi.org/10.1109/ddecs.2006.1649606openalex-snapshot

Can clock faults be detected through functional test?

inferred← citeshttps://doi.org/10.1109/icsict.2010.5667704openalex-snapshot

Testability design of motor control digital signal processor

inferred← citeshttps://doi.org/10.1109/iolts.2006.47openalex-snapshot

Path (min) delay faults and their impact on self-checking circuits operation

inferred← citeshttps://doi.org/10.1109/tc.2006.22openalex-snapshot

Debug support strategy for systems-on-chips with multiple processor cores

inferred← citeshttps://doi.org/10.1109/tc.2007.53openalex-snapshot

Won't On-Chip Clock Calibration Guarantee Performance Boost and Product Quality?

inferred← citeshttps://doi.org/10.1109/tcsii.2010.2049923openalex-snapshot

A Scan Cell Design for Scan-Based Debugging of an SoC With Multiple Clock Domains

inferred← citeshttps://doi.org/10.1109/te.2004.832880openalex-snapshot

Integrating Formal Verification into an Advanced Computer Architecture Course

inferred← citeshttps://doi.org/10.1109/test.2003.1270905openalex-snapshot

Latch divergency in microprocessor failure analysis

inferred← citeshttps://doi.org/10.1109/test.2004.1387395openalex-snapshot

Risks associated with faults within test pattern compactors and their implications on testing

inferred← citeshttps://doi.org/10.1145/977091.977153openalex-snapshot

Fault secureness need for next generation high performance microprocessor design for testability structures

inferred← citeshttps://doi.org/10.14288/1.0067636openalex-snapshot

Practical considerations for post-silicon debug using backspace

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