On the public citation graph
Debug support strategy for systems-on-chips with multiple processor cores
0 signed · 82 inferred · view as graph
Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.
Is this your work? Sign in with ORCID and put your name on the
claims that are yours.
Reference health. See whether every reference in this work resolves to a
known work and none has been retracted — and get a dated CiteStamped
badge you can embed.
What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1049/cce:20000608openalex-snapshot
Emerging on-ship debugging techniques for real-time embedded systems
inferredcites →https://doi.org/10.1109/2.769444openalex-snapshot
Testing embedded-core-based system chips
inferredcites →https://doi.org/10.1109/2.976921openalex-snapshot
Networks on chips: a new SoC paradigm
inferredcites →https://doi.org/10.1109/date.2005.109openalex-snapshot
Debug Support, Calibration and Emulation for Multiple Processor and Powertrain Control SoCs
inferredcites →https://doi.org/10.1109/ieeestd.2013.6515989openalex-snapshot
IEEE Standard for Test Access Port and Boundary-Scan Architecture
inferredcites →https://doi.org/10.1109/iscas.2003.1206375openalex-snapshot
On-chip debug support for embedded Systems-on-Chip
inferredcites →https://doi.org/10.1109/mc.2007.118openalex-snapshot
Boosting Debugging Support for Complex Systems on Chip
inferredcites →https://doi.org/10.1109/test.2000.894201openalex-snapshot
Test and on-line debug capabilities of IEEE Std 1149.1 in UltraSPARC/sup TM/-III microprocessor
inferredcites →https://doi.org/10.1109/test.2000.894273openalex-snapshot
On using IEEE P1500 SECT for test plug-n-play
inferredcites →https://doi.org/10.1109/test.2002.1041745openalex-snapshot
IEEE 1149.1-compliant access architecture for multiple core debug on digital system chips
inferredcites →https://doi.org/10.13140/rg.2.1.2013.9606openalex-snapshot
The Test Access Port and Boundary-Scan Architecture
inferredcites →https://doi.org/10.4271/2003-01-1035openalex-snapshot
Real Time Calibration and Debug Techniques of Embedded Processors with the Nexus 5001 Interface
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/11946441_73openalex-snapshot
TraceDo: An On-Chip Trace System for Real-Time Debug and Optimization in Multiprocessor SoC
inferred← citeshttps://doi.org/10.1007/978-3-319-30695-7_15openalex-snapshot
DiaSys: On-Chip Trace Analysis for Multi-processor System-on-Chip
inferred← citeshttps://doi.org/10.1007/978-3-540-72685-2_7openalex-snapshot
Scheduling for Combining Traffic of On-Chip Trace Data in Embedded Multi-core Processor
inferred← citeshttps://doi.org/10.1007/978-981-13-2553-3_47openalex-snapshot
A Novel Method to Detect Program Malfunctioning on Embedded Devices Using Run-Time Trace
inferred← citeshttps://doi.org/10.1007/s10617-014-9135-8openalex-snapshot
Design methodology for on-chip-based processor debugger
inferred← citeshttps://doi.org/10.1016/j.sysarc.2010.07.005openalex-snapshot
Embedded software debugging using virtual filesystem abstractions
inferred← citeshttps://doi.org/10.1016/j.sysarc.2015.07.007openalex-snapshot
Exploring ICMetrics to detect abnormal program behaviour on embedded devices
inferred← citeshttps://doi.org/10.1016/j.sysarc.2017.01.005openalex-snapshot
DiaSys: Improving SoC insight through on-chip diagnosis
inferred← citeshttps://doi.org/10.1049/iet-sen.2011.0212openalex-snapshot
On‐chip support for software verification and debug in multi‐core embedded systems
inferred← citeshttps://doi.org/10.1049/ip-cdt:20050194openalex-snapshot
Debug support for complex systems on-chip: a review
inferred← citeshttps://doi.org/10.1109/ahs.2006.34openalex-snapshot
ESPACENET: A Framework of Evolvable and Reconfigurable Sensor Networks for Aerospace–Based Monitoring and Diagnostics
inferred← citeshttps://doi.org/10.1109/ahs.2006.4openalex-snapshot
A Generic On-Chip Debugger for Wireless Sensor Networks
inferred← citeshttps://doi.org/10.1109/ahs.2007.106openalex-snapshot
Trace algorithms for deeply integrated complex and hybrid SoCs
inferred← citeshttps://doi.org/10.1109/ahs.2007.107openalex-snapshot
TRICODA - Complex Data Analysis and Condition Monitoring based onv Neural Network Model
inferred← citeshttps://doi.org/10.1109/ahs.2007.18openalex-snapshot
A System Level Framework for Monitoring and Self Diagnosis in ESPACENET
inferred← citeshttps://doi.org/10.1109/ahs.2007.48openalex-snapshot
Ensuring data integrity via ICmetrics based security infrastructure
inferred← citeshttps://doi.org/10.1109/ahs.2008.8openalex-snapshot
Adaptive Online Profiling Hardware for ICmetrics Based Security
inferred← citeshttps://doi.org/10.1109/date.2007.364595openalex-snapshot
Low Cost Debug Architecture using Lossy Compression for Silicon Debug
inferred← citeshttps://doi.org/10.1109/est.2012.23openalex-snapshot
ICmetrics for Low Resource Embedded Systems
inferred← citeshttps://doi.org/10.1109/ets.2008.29openalex-snapshot
On Bypassing Blocking Bugs during Post-Silicon Validation
inferred← citeshttps://doi.org/10.1109/hpca.2011.5749740openalex-snapshot
Hardware/software-based diagnosis of load-store queues using expandable activity logs
inferred← citeshttps://doi.org/10.1109/icasic.2007.4415798openalex-snapshot
A hardware approach to reconfigurable lossless real-time tracer
inferred← citeshttps://doi.org/10.1109/icicdt.2007.4299586openalex-snapshot
Cell BE SOC Debug Features
inferred← citeshttps://doi.org/10.1109/icm.2007.4497679openalex-snapshot
Assertion-based debug infrastructure for SoC designs
inferred← citeshttps://doi.org/10.1109/imtc.2006.235970openalex-snapshot
Instrumentation of Real-Time Embedded Systems for Performance Analysis
inferred← citeshttps://doi.org/10.1109/imtc.2007.379044openalex-snapshot
Optoelectronic Measurement Interface for System-on-Chip Debug
inferred← citeshttps://doi.org/10.1109/iscas.2006.1692870openalex-snapshot
Debug support for embedded processor reuse
inferred← citeshttps://doi.org/10.1109/iscit.2007.4392004openalex-snapshot
Reconfigurable On-Chip Debugger with a real-time tracer
inferred← citeshttps://doi.org/10.1109/iscit.2007.4392005openalex-snapshot
Implementation and analysis of configurable Real Time Address Trace Compressor for embedded microprocessors
inferred← citeshttps://doi.org/10.1109/lascas.2011.5750280openalex-snapshot
Backend for virtual platforms with hardware scheduler in the MAPS framework
inferred← citeshttps://doi.org/10.1109/mdt.2009.53openalex-snapshot
Comprehensive Approach to High-Performance Server Chipset Debug
inferred← citeshttps://doi.org/10.1109/mtv.2006.7openalex-snapshot
Debug Support for Scalable System-on-Chip
inferred← citeshttps://doi.org/10.1109/rsp.2011.5929983openalex-snapshot
A non intrusive simulation-based trace system to analyse Multiprocessor Systems-on-Chip software
inferred← citeshttps://doi.org/10.1109/snpd.2007.178openalex-snapshot
Assessment on Fault-tolerance Performance Using Neural Network Model Based on Ant Colony Optimization Algorithm for Fault Diagnosis in Distribution Systems of Electric Power Systems
inferred← citeshttps://doi.org/10.1109/snpd.2007.183openalex-snapshot
Chinese Question Classification Based on Ensemble Learning
inferred← citeshttps://doi.org/10.1109/tc.2010.122openalex-snapshot
On Using Lossy Compression for Repeatable Experiments during Silicon Debug
inferred← citeshttps://doi.org/10.1109/tc.2010.146openalex-snapshot
Caches and Predictors for Real-Time, Unobtrusive, and Cost-Effective Program Tracing in Embedded Systems
inferred← citeshttps://doi.org/10.1109/tc.2010.194openalex-snapshot
A Trace-Capable Instruction Cache for Cost-Efficient Real-Time Program Trace Compression in SoC
inferred← citeshttps://doi.org/10.1109/tcad.2017.2778084openalex-snapshot
On Trace Buffer Reuse-Based Trigger Generation in Post-Silicon Debug
inferred← citeshttps://doi.org/10.1109/tcsi.2006.887613openalex-snapshot
A Hardware Approach to Real-Time Program Trace Compression for Embedded Processors
inferred← citeshttps://doi.org/10.1109/tcsi.2014.2334892openalex-snapshot
A Versatile Data Cache for Trace Buffer Support
inferred← citeshttps://doi.org/10.1109/test.2006.297671openalex-snapshot
Debug of the CELL Processor: Moving the Lab into Silicon
inferred← citeshttps://doi.org/10.1109/test.2007.4437613openalex-snapshot
On using lossless compression of debug data in embedded logic analysis
inferred← citeshttps://doi.org/10.1109/tifs.2015.2422674openalex-snapshot
A Method for Detecting Abnormal Program Behavior on Embedded Devices
inferred← citeshttps://doi.org/10.1109/tvlsi.2007.896905openalex-snapshot
First Silicon Functional Validation and Debug of Multicore Microprocessors
inferred← citeshttps://doi.org/10.1109/tvlsi.2009.2014872openalex-snapshot
A Reverse-Encoding-Based On-Chip Bus Tracer for Efficient Circular-Buffer Utilization
inferred← citeshttps://doi.org/10.1109/tvlsi.2009.2038390openalex-snapshot
Embedded Debug Architecture for Bypassing Blocking Bugs During Post-Silicon Validation
inferred← citeshttps://doi.org/10.1109/tvlsi.2009.2039811openalex-snapshot
An On-Chip AHB Bus Tracer With Real-Time Compression and Dynamic Multiresolution Supports for SoC
inferred← citeshttps://doi.org/10.1145/1278480.1278604openalex-snapshot
An embedded multi-resolution AMBA trace analyzer for microprocessor-based SoC integration
inferred← citeshttps://doi.org/10.1145/1391469.1391688openalex-snapshot
An embedded infrastructure of debug and trace interface for the DSP platform
inferred← citeshttps://doi.org/10.1145/1629911.1629952openalex-snapshot
A trace-capable instruction cache for cost efficient real-time program trace compression in SoC
inferred← citeshttps://doi.org/10.1145/1878921.1878938openalex-snapshot
Real-time unobtrusive program execution trace compression using branch predictor events
inferred← citeshttps://doi.org/10.1145/1878921.1878940openalex-snapshot
Hardware-based data value and address trace filtering techniques
inferred← citeshttps://doi.org/10.1145/2442087.2442088openalex-snapshot
A survey and taxonomy of on-chip monitoring of multicore systems-on-chip
inferred← citeshttps://doi.org/10.1145/2693433.2693437openalex-snapshot
Collecting traces in dynamic binary translation based virtual prototyping platforms
inferred← citeshttps://doi.org/10.1145/2766449openalex-snapshot
Architecture-Aware Real-Time Compression of Execution Traces
inferred← citeshttps://doi.org/10.1145/3322642openalex-snapshot
Enabling On-the-Fly Hardware Tracing of Data Reads in Multicores
inferred← citeshttps://doi.org/10.13140/rg.2.2.30539.90403openalex-snapshot
TECHNIQUES FOR CAPTURING AND FILTERING DATA VALUE TRACES IN MULTICORES
inferred← citeshttps://doi.org/10.34961/3542openalex-snapshot
Utilizing multicore architectures to enhance software verification in real-time embedded systems
inferred← citeshttps://doi.org/10.4218/etrij.11.0111.0172openalex-snapshot
On-Chip Debug Architecture for Multicore Processor
inferred← citeshttps://doi.org/10.4218/etrij.12.0112.0487openalex-snapshot
Easily Adaptable On-Chip Debug Architecture for Multicore Processors
inferred← citeshttps://doi.org/10.5555/1266366.1266414openalex-snapshot
Interactive presentation: Low cost debug architecture using lossy compression for silicon debug
inferred← citeshttps://doi.org/10.5555/1509633.1509796openalex-snapshot
A reverse-encoding-based on-chip AHB bus tracer for efficient circular buffer utilization
inferred← citeshttps://doi.org/10.71548/17175openalex-snapshot
New Algorithms and Architectures for Post-Silicon Validation
inferred← citeshttps://doi.org/10.71548/17589openalex-snapshot
ON-CHIP DEBUG ARCHITECTURES FOR IMPROVING OBSERVABILITY DURING POST-SILICON VALIDATION
inferred← citeshttps://doi.org/10.7753/ijcatr0301.1017openalex-snapshot
An AMBA Advanced High performance Bus Tracer with Real time Compression for Support of SoC
inferred← citeshttps://doi.org/10.7873/date2014.199openalex-snapshot
Scalability bottlenecks discovery in MPSoC platforms using data mining on simulation traces
Editorial review for independent work. ICSAC — the Institute for Complexity
Science and Advanced Computing — runs a structured editorial panel for researchers
publishing outside journals, and publishes on CiteStamp rails. Submission is free
and goes through ORCID: icsacinstitute.org/submit.