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The effect of context switches on cache performance

https://doi.org/10.1145/106972.106982
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1109/12.40842openalex-snapshot
Evaluating associativity in CPU caches
inferredcites →https://doi.org/10.1109/2.16openalex-snapshot
The Sprite network operating system
inferredcites →https://doi.org/10.1109/iccd.1989.63361openalex-snapshot
Integration and packaging plateaus of processor performance
inferredcites →https://doi.org/10.1145/106972.106985openalex-snapshot
The interaction of architecture and operating system design
inferredcites →https://doi.org/10.1145/106972.106991openalex-snapshot
Limits of instruction-level parallelism
inferredcites →https://doi.org/10.1145/106975.106985openalex-snapshot
The interaction of architecture and operating system design
inferredcites →https://doi.org/10.1145/107971.107994openalex-snapshot
MTOOL
inferredcites →https://doi.org/10.1145/113445.113451openalex-snapshot
Predicting program behavior using real or estimated profiles
inferredcites →https://doi.org/10.1145/205447.205456openalex-snapshot
Fragmentation considered harmful
inferredcites →https://doi.org/10.1145/205447.205460openalex-snapshot
Measured capacity of an Ethernet
inferredcites →https://doi.org/10.1145/214451.214455openalex-snapshot
Performance of the VAX-11/780 translation buffer
inferredcites →https://doi.org/10.1145/285930.285998openalex-snapshot
Improving direct-mapped cache performance by the addition of a small fully-associative cache prefetch buffers
inferredcites →https://doi.org/10.1145/29868.32979openalex-snapshot
Footprints in the cache
inferredcites →https://doi.org/10.1145/325096.325153openalex-snapshot
Generation and analysis of very long address traces
inferredcites →https://doi.org/10.1145/325164.325153openalex-snapshot
Generation and analysis of very long address traces
inferredcites →https://doi.org/10.1145/356887.356892openalex-snapshot
Cache Memories
inferredcites →https://doi.org/10.1145/37888.38004openalex-snapshot
Fast printed circuit board routing
inferredcites →https://doi.org/10.1145/48012.48037openalex-snapshot
Cache performance of operating system and multiprogramming workloads
inferredcites →https://doi.org/10.1145/63404.63407openalex-snapshot
An analytical cache model
inferredcites →https://doi.org/10.1145/68182.68200openalex-snapshot
Program optimization for instruction caches
inferredcites →https://doi.org/10.1145/70082.68200openalex-snapshot
Program optimization for instruction caches
inferredcites →https://doi.org/10.1145/74850.74861openalex-snapshot
Lightweight remote procedure call
inferredcites →https://doi.org/10.1145/74851.74861openalex-snapshot
Lightweight remote procedure call
inferredcites →https://doi.org/10.1145/74925.74957openalex-snapshot
Architectural and organizational tradeoffs in the design of the MultiTitan CPU
inferredcites →https://doi.org/10.1145/75108.75380openalex-snapshot
TRAPEDS: producing traces for multicomputers via execution driven simulation
inferredcites →https://doi.org/10.1145/75372.75380openalex-snapshot
TRAPEDS: producing traces for multicomputers via execution driven simulation
inferredcites →https://doi.org/10.1145/77648.77650openalex-snapshot
Lightweight remote procedure call
inferredcites →https://doi.org/10.1145/989393.989415openalex-snapshot
Global register allocation at link time
inferredcites →https://doi.org/10.1145/989393.989422openalex-snapshot
Register windows vs. register allocation

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

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ATOM
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Adaptive code unloading for resource-constrained JVMs
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Observations on Power-Efficiency Trends in Mobile Communication Devices
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iWARP-based high-definition media dissemination
inferred← citeshttps://doi.org/10.4995/thesis/10251/55328openalex-snapshot
Utilización de memorias cache con bloqueo en sistemas de tiempo real.
inferred← citeshttps://doi.org/10.5220/0004455200050014openalex-snapshot
Simulation of Real-time Multiprocessor Scheduling with Overheads
inferred← citeshttps://doi.org/10.5555/1715759.1715772openalex-snapshot
A cross-layer approach to heterogeneity and reliability
inferred← citeshttps://doi.org/10.5555/1924943.1924946openalex-snapshot
FlexSC: flexible system call scheduling with exception-less system calls
inferred← citeshttps://doi.org/10.5555/259794.259872openalex-snapshot
Boolean matching for full-custom ECL gates
inferred← citeshttps://doi.org/10.5555/266800.266813openalex-snapshot
Exploiting dead value information
inferred← citeshttps://doi.org/10.70675/98f02e40zdcd3z4e48z8823z93fd654bfc4aopenalex-snapshot
Cache-conscious off-line real-time scheduling for multi-core platforms : algorithms and implementation
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