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The interaction of architecture and operating system design
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1002/spe.4380180802openalex-snapshot
PRESTO: A system for object‐oriented parallel programming
inferredcites →https://doi.org/10.1109/12.40843openalex-snapshot
The performance implications of thread management alternatives for shared-memory multiprocessors
inferredcites →https://doi.org/10.1109/12.4607openalex-snapshot
Implementing precise interrupts in pipelined processors
inferredcites →https://doi.org/10.1109/ms.1984.234046openalex-snapshot
The V Kernel: A Software Base for Distributed Systems
inferredcites →https://doi.org/10.1145/103720.114701openalex-snapshot
User-level interprocess communication for shared memory multiprocessors
inferredcites →https://doi.org/10.1145/13310.13338openalex-snapshot
Global register allocation at link time
inferredcites →https://doi.org/10.1145/2080.357392openalex-snapshot
Implementing remote procedure calls
inferredcites →https://doi.org/10.1145/214419.214422openalex-snapshot
The integration of virtual memory management and interprocess communication in Accent
inferredcites →https://doi.org/10.1145/214451.214455openalex-snapshot
Performance of the VAX-11/780 translation buffer
inferredcites →https://doi.org/10.1145/36204.36199openalex-snapshot
Firefly: a multiprocessor workstation
inferredcites →https://doi.org/10.1145/37499.37507openalex-snapshot
The duality of memory and communication in the implementation of a multiprocessor operating system
inferredcites →https://doi.org/10.1145/41457.37507openalex-snapshot
The duality of memory and communication in the implementation of a multiprocessor operating system
inferredcites →https://doi.org/10.1145/4472.4478openalex-snapshot
MULTILISP: a language for concurrent symbolic computation
inferredcites →https://doi.org/10.1145/48012.48037openalex-snapshot
Cache performance of operating system and multiprogramming workloads
inferredcites →https://doi.org/10.1145/54289.54291openalex-snapshot
Performance of the world's fastest distributed operating system
inferredcites →https://doi.org/10.1145/633625.52446openalex-snapshot
The VMP multiprocessor: initial experience, refinements, and performance evaluation
inferredcites →https://doi.org/10.1145/641914.641917openalex-snapshot
The case for the reduced instruction set computer
inferredcites →https://doi.org/10.1145/74850.74869openalex-snapshot
Threads and input/output in the synthesis kernal
inferredcites →https://doi.org/10.1145/74851.74861openalex-snapshot
Lightweight remote procedure call
inferredcites →https://doi.org/10.1145/75104.75105openalex-snapshot
Memory coherence in shared virtual memory systems
inferredcites →https://doi.org/10.1145/77648.77650openalex-snapshot
Lightweight remote procedure call
inferredcites →https://doi.org/10.1145/800050.801820openalex-snapshot
Hardware/software tradeoffs for increased performance
inferredcites →https://doi.org/10.1145/960112.28705openalex-snapshot
Mach and Matchmaker: kernel and language support for object-oriented distributed systems
inferredcites →https://doi.org/10.1145/989393.989415openalex-snapshot
Global register allocation at link time
inferredcites →https://doi.org/10.1145/989393.989417openalex-snapshot
Real-time concurrent collection on stock multiprocessors
inferredcites →https://doi.org/10.1145/99163.99173openalex-snapshot
Real-time, concurrent checkpoint for parallel programs
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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Synchronous/Reactive Programming of Concurrent System Software
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Application Program Interfaces
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Kernel‐Kernel communication in a shared‐memory multiprocessor
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Experiences with networked parallel computing
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The peregrine high‐performance RPC system
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Object identification in the lego kernel
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Improving the Precise Interrupt Mechanism of Software- Managed TLB Miss Handlers
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Panda — Supporting Distributed Programming in C++
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Object- and Memory-Management Architecture
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Efficient compile-time/run-time contraction of fine grain data parallel codes
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Mercury: Object-affinity scheduling and continuation passing on multiprocessors
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A Simulation-Based Study on Memory Design Issues for Embedded Systems
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Betriebssysteme für Parallelrechner
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Improving Server Performance on Multi-cores via Selective Off-Loading of OS Functionality
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Quantitative analysis of hardware support for real-time operating systems
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The SpectrumWare approach to wireless signal processing
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A new architecture design paradigm for parallel computing in scheme
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Evaluation of multithreaded processors and thread-switch policies
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Operating system support for high-performance architectures
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Analysing communication latency using the Nectar communication processor
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Scalable approaches to load sharing in the presence of multicasting
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Fast context switches: compiler and architectural support for preemptive scheduling
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A software-controlled prefetching mechanism for software-managed TLBs
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Reducing cache and TLB power by exploiting memory region and privilege level semantics
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Supporting parallel applications on clusters of workstations: The Virtual Communication Machine‐based architecture
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Performance study of some symmetric block cipher algorithms under Linux operating system
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Multi-View Memory Support to Operating Systems in Locking for Transaction and Database Systems
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Optimizing the instruction cache performance of the operating system
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Comprehensive hardware and software support for operating systems to exploit MP memory hierarchies
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Concurrent event handling through multithreading
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Uniprocessor virtual memory without TLBs
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Engineering and analysis of fixed priority schedulers
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Cache performance of the SPEC92 benchmark suite
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Designing SSI clusters with hierarchical checkpointing and single I/O space
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The VuSystem: a programming system for compute-intensive multimedia
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Quantitative characterization and analysis of the I/O behavior of a commercial distributed-shared-memory machine
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Access control protocols for multi-view on-the-fly memory computer system
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Performance Characterization and Optimization of Atomic Operations on AMD GPUs
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The Midway distributed shared memory system
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Practical techniques for damage confinement in software
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A protection cache architecture for the multi-view memory model and its performance
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DPGA-coupled microprocessors: commodity ICs for the early 21st Century
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Resource-driven resource location
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Architectural support for synchronization of threads accessing variable-sized units of virtual memory
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Real-time operating systems for multimedia processing
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Double context microprocessor architecture
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Optimizing instruction cache performance for operating system intensive workloads
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Software cache coherence for large scale multiprocessors
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Improving the data cache performance of multiprocessor operating systems
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Protected, user-level DMA for the SHRIMP network interface
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Design issues and tradeoffs for write buffers
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Software-managed address translation
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Serializing instructions in system-intensive workloads: Amdahl’s Law strikes again
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Effect of task allocation methods for mesh-connected parallel computers considering task size limitation and machine size extension
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In-line interrupt handling for software-managed TLBs
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Cost-effective graceful degradation in speculative processor subsystems: the branch prediction case
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Inconsistency in translation lookaside buffer
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Multi-view memory to support OS locking for transaction systems
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Performance analysis of the memory management unit under scale-out workloads
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NOISEMINER: An algorithm for scalable automatic computational noise and software interference detection
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Evaluating the Impact of TLB Misses on Future HPC Systems
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Design Tradeoffs For Software-managed Tlbs
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Multiple Threads In Cyclic Register Windows
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Optimal allocation of on-chip memory for multiple-API operating systems
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Going the distance for TLB prefetching: an application-driven study
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Exploiting Page Table Locality for Agile TLB Prefetching
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Operating system support for small objects
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Host interface design for ATM LANs
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Strategies for using multicasting to locate resources
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Exploiting dead value information
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Efficient object-oriented execution strategies for parallel computers
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Characterizing the TLB Behavior of Emerging Parallel Workloads on Chip Multiprocessors
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Load sharing using multicasting
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Hardware Support for Safety Interlocks and Introspection
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Reducing the variance of point to point transfers in the IBM 9076 parallel computer
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Concurrent support of multiple page sizes on a skewed associative TLB
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In-line interrupt handling and lock-up free translation lookaside buffers (TLBs)
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Recent advances in TRON-spec. chips
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Dynamic Aggregation of Virtual Addresses in TLB Using TCAM Cells
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Opal: a single address space system for 64-bit architecture address space
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The persistent relevance of IPC performance: new techniques for reducing the IPC penalty
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Software methods for system address tracing
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The effect of context switches on cache performance
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Performance from architecture: comparing a RISC and a CISC with similar hardware organization
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The effect of context switches on cache performance
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Performance from architecture: comparing a RISC and a CISC with similar hardware organization
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The effect of context switches on cache performance
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Performance from architecture: comparing a RISC and a CISC with similar hardware organization
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The effect of context switches on cache performance
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Performance from architecture: comparing a RISC and a CISC with similar hardware organization
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Deconstructing process isolation
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The implications of cache affinity on processor scheduling for multiprogrammed, shared memory multiprocessors
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The implications of cache affinity on processor scheduling for multiprogrammed, shared memory multiprocessors
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A comparison of the effect of branch prediction on multithreaded and scalar architectures
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The effects of virtually addressed caches on virtual memory design and performance
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Characterizing the caching and synchronization performance of a multiprocessor operating system
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Architecture support for single address space operating systems
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Fast mutual exclusion for uniprocessors
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Characterizing the caching and synchronization performance of a multiprocessor operating system
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Fast mutual exclusion for uniprocessors
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Analyzing communication latency using the Nectar communication processor
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Analyzing communication latency using the Nectar communication processor
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Porting OpenVMS from VAX to Alpha AXP
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Limits to low-latency communication on high-speed networks
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Designing and implementingChoices
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Recent trends in experimental operating systems research
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Design tradeoffs for software-managed TLBs
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Multiple threads in cyclic register windows
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Processor scheduling on multiprogrammed, distributed memory parallel computers
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Processor scheduling on multiprogrammed, distributed memory parallel computers
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Protection traps and alternatives for memory management of an object-oriented language
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The impact of operating system structure on memory system performance
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Efficient software-based fault isolation
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Inter-core cooperative TLB for chip multiprocessors
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Inter-core cooperative TLB for chip multiprocessors
inferred← citeshttps://doi.org/10.1145/1736020.1736060openalex-snapshot
Inter-core cooperative TLB for chip multiprocessors
inferred← citeshttps://doi.org/10.1145/173668.168628openalex-snapshot
Protection traps and alternatives for memory management of an object-oriented language
inferred← citeshttps://doi.org/10.1145/173668.168629openalex-snapshot
The impact of operating system structure on memory system performance
inferred← citeshttps://doi.org/10.1145/173668.168635openalex-snapshot
Efficient software-based fault isolation
inferred← citeshttps://doi.org/10.1145/173682.165127openalex-snapshot
Design tradeoffs for software-managed TLBs
inferred← citeshttps://doi.org/10.1145/173682.165149openalex-snapshot
Multiple threads in cyclic register windows
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Design tradeoffs for software-managed TLBs
inferred← citeshttps://doi.org/10.1145/191995.192070openalex-snapshot
Optimal allocation of on-chip memory for multiple-API operating systems
inferred← citeshttps://doi.org/10.1145/192007.192070openalex-snapshot
Optimal allocation of on-chip memory for multiple-API operating systems
inferred← citeshttps://doi.org/10.1145/195470.195515openalex-snapshot
Hardware and software support for efficient exception handling
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Trap-driven simulation with Tapeworm II
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Hardware and software support for efficient exception handling
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Trap-driven simulation with Tapeworm II
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The operating system kernel as a secure programmable machine
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Objects to the rescue! or httpd : the next generation operating system
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User-level threads on a general hardware interface
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Extensibility safety and performance in the SPIN operating system
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Extensibility safety and performance in the SPIN operating system
inferred← citeshttps://doi.org/10.1145/232973.232994openalex-snapshot
Evaluation of multithreaded uniprocessors for commercial application environments
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Evaluation of multithreaded uniprocessors for commercial application environments
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Whole-program optimization for time and space efficient threads
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Trap-driven memory simulation with Tapeworm II
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Whole-program optimization for time and space efficient threads
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Whole-program optimization for time and space efficient threads
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File server scaling with network-attached secure disks
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File server scaling with network-attached secure disks
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Free transactions with Rio Vista
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Extensible security architectures for Java
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Free transactions with Rio Vista
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Extensible security architectures for Java
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Improving applications performance
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Effect of TLB on system performance
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A look at several memory management units, TLB-refill mechanisms, and page table organizations
inferred← citeshttps://doi.org/10.1145/291069.291065openalex-snapshot
A look at several memory management units, TLB-refill mechanisms, and page table organizations
inferred← citeshttps://doi.org/10.1145/3341301.3359640openalex-snapshot
An analysis of performance evolution of Linux's core operations
inferred← citeshttps://doi.org/10.1145/3613424.3614276openalex-snapshot
Victima: Drastically Increasing Address Translation Reach by Leveraging Underutilized Cache Resources
inferred← citeshttps://doi.org/10.1145/3613424.3623789openalex-snapshot
Utopia: Fast and Efficient Address Translation via Hybrid Restrictive & Flexible Virtual-to-Physical Address Mappings
inferred← citeshttps://doi.org/10.1145/3676641.3716027openalex-snapshot
Virtuoso: Enabling Fast and Accurate Virtual Memory Research via an Imitation-based Operating System Simulation Methodology
inferred← citeshttps://doi.org/10.1145/381792.195515openalex-snapshot
Hardware and software support for efficient exception handling
inferred← citeshttps://doi.org/10.1145/381792.195521openalex-snapshot
Trap-driven simulation with Tapeworm II
inferred← citeshttps://doi.org/10.1145/384265.291065openalex-snapshot
A look at several memory management units, TLB-refill mechanisms, and page table organizations
inferred← citeshttps://doi.org/10.1145/504390.504407openalex-snapshot
The operating system kernel as a secure programmable machine
inferred← citeshttps://doi.org/10.1145/511334.511351openalex-snapshot
Characterizing the d -TLB behavior of SPEC CPU2000 benchmarks
inferred← citeshttps://doi.org/10.1145/511399.511351openalex-snapshot
Characterizing the d -TLB behavior of SPEC CPU2000 benchmarks
inferred← citeshttps://doi.org/10.1145/545214.545237openalex-snapshot
Going the distance for TLB prefetching
inferred← citeshttps://doi.org/10.1145/605397.605405openalex-snapshot
Understanding and improving operating system effects in control flow prediction
inferred← citeshttps://doi.org/10.1145/605432.605405openalex-snapshot
Understanding and improving operating system effects in control flow prediction
inferred← citeshttps://doi.org/10.1145/635506.605405openalex-snapshot
Understanding and improving operating system effects in control flow prediction
inferred← citeshttps://doi.org/10.1145/635508.605405openalex-snapshot
Understanding and improving operating system effects in control flow prediction
inferred← citeshttps://doi.org/10.1145/997163.997184openalex-snapshot
Measuring the cache interference cost in preemptive real-time systems
inferred← citeshttps://doi.org/10.1145/997163.997186openalex-snapshot
Adaptive code unloading for resource-constrained JVMs
inferred← citeshttps://doi.org/10.1145/998300.997184openalex-snapshot
Measuring the cache interference cost in preemptive real-time systems
inferred← citeshttps://doi.org/10.1145/998300.997186openalex-snapshot
Adaptive code unloading for resource-constrained JVMs
inferred← citeshttps://doi.org/10.1147/rd.355.0653openalex-snapshot
The Parallel Processing Compute Server
inferred← citeshttps://doi.org/10.1184/r1/6604457openalex-snapshot
Continuations : unifying thread management and communication in operating systems
inferred← citeshttps://doi.org/10.1184/r1/6607622openalex-snapshot
Mutual exclusion for uniprocessors
inferred← citeshttps://doi.org/10.21236/ada256222openalex-snapshot
Transactional Distributed Shared Memory
inferred← citeshttps://doi.org/10.21236/ada266638openalex-snapshot
Fast Interrupt Priority Management in Operating System Kernels
inferred← citeshttps://doi.org/10.21236/ada341735openalex-snapshot
Active Disks - Remote Execution for Network-Attached Storage,
inferred← citeshttps://doi.org/10.46632/daai/1/1/10openalex-snapshot
Evaluation of Operating System Using Electric Multi Criteria Decision Making Method
inferred← citeshttps://doi.org/10.5555/1267638.1267648openalex-snapshot
Performance issues in parallelized network protocols
inferred← citeshttps://doi.org/10.5555/1267638.1267656openalex-snapshot
Software prefetching and caching for translation lookaside buffers
inferred← citeshttps://doi.org/10.5555/266800.266813openalex-snapshot
Exploiting dead value information
inferred← citeshttps://doi.org/10.5555/602770.602873openalex-snapshot
Reducing the variance of point to point transfers in the IBM 9076 parallel computer
inferred← citeshttps://doi.org/10.5821/dissertation-2117-95290openalex-snapshot
Scalable system software for high performance large-scale applications
inferred← citeshttps://doi.org/10.5821/dissertation-2117-96333openalex-snapshot
Improving the performance and energy-efficiency of virtual memory
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