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Integrating register allocation and instruction scheduling for RISCs

https://doi.org/10.1145/106972.106986
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1002/spe.4380090307openalex-snapshot
Unrolling loops in fortran
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A code generation interface for ANSI C
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Trace Scheduling: A Technique for Global Microcode Compaction
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Optimizing delayed branches
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The Marion system for retargetable instruction scheduling
inferredcites →https://doi.org/10.1145/115952.115985openalex-snapshot
The effect on RISC performance of register set size and structure versus code generation strategy
inferredcites →https://doi.org/10.1145/2166.357217openalex-snapshot
Postpass Code Optimization of Pipeline Constraints
inferredcites →https://doi.org/10.1145/2591635.2667158openalex-snapshot
Code scheduling and register allocation in large basic blocks
inferredcites →https://doi.org/10.1145/36204.36191openalex-snapshot
A study of scalar compilation techniques for pipelined supercomputers
inferredcites →https://doi.org/10.1145/502874.502896openalex-snapshot
Register allocation by priority-based coloring
inferredcites →https://doi.org/10.1145/800230.806984openalex-snapshot
Register allocation & spilling via graph coloring
inferredcites →https://doi.org/10.1145/872726.806984openalex-snapshot
Register allocation & spilling via graph coloring
inferredcites →https://doi.org/10.1145/989393.989413openalex-snapshot
Efficient instruction scheduling for a pipelined architecture
inferredcites →https://doi.org/10.1145/989393.989424openalex-snapshot
Coloring heuristics for register allocation
inferredcites →https://doi.org/10.1147/rd.111.0025openalex-snapshot
An Efficient Algorithm for Exploiting Multiple Arithmetic Units

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

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