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Performance from architecture: comparing a RISC and a CISC with similar hardware organization
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
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Designing a VAX for high performance
inferredcites →https://doi.org/10.1145/106972.106985openalex-snapshot
The interaction of architecture and operating system design
inferredcites →https://doi.org/10.1145/2465.214917openalex-snapshot
Reduced instruction set computers
inferredcites →https://doi.org/10.1145/285930.285986openalex-snapshot
A characterization of processor performance in the VAX-11/780
inferredcites →https://doi.org/10.1145/30350.30352openalex-snapshot
An evaluation of branch architectures
inferredcites →https://doi.org/10.1145/42392.42394openalex-snapshot
The search for performance in scientific processors: the Turing Award lecture
inferredcites →https://doi.org/10.1145/633625.52421openalex-snapshot
Measuring VAX 8800 performance with a histogram hardware monitor
inferredcites →https://doi.org/10.1145/68182.68207openalex-snapshot
Available instruction-level parallelism for superscalar and superpipelined machines
inferredcites →https://doi.org/10.1145/68182.68209openalex-snapshot
Limits on multiple instruction issue
inferredcites →https://doi.org/10.1145/88237.88243openalex-snapshot
Cache performance of the integer SPEC benchmarks on a RISC
inferredcites →https://doi.org/10.1147/rd.341.0004openalex-snapshot
The evolution of RISC technology at IBM
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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Reduced Instruction Set Computing
inferred← citeshttps://doi.org/10.1002/9780470050118.ecse357openalex-snapshot
Reduced Instruction Set Computing
inferred← citeshttps://doi.org/10.1007/11802839_36openalex-snapshot
PISC: Polymorphic Instruction Set Computers
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Polymorphic Instruction Set Computers
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A Survey on the Software and Hardware-Based Influences on the Worst-Case Execution Time
inferred← citeshttps://doi.org/10.1007/978-3-540-93799-9_4openalex-snapshot
A Tale of Two Processors: Revisiting the RISC-CISC Debate
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Maximal and near-maximal shift register sequences: efficient event counters and easy discrete logarithms
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An architectural framework for supporting heterogeneous instruction-set architectures
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Operating Systems Portability: 8 bits and beyond
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PERL-a registerless architecture
inferred← citeshttps://doi.org/10.1109/hpca.2013.6522302openalex-snapshot
Power struggles: Revisiting the RISC vs. CISC debate on contemporary ARM and x86 architectures
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Characterization of Alpha AXP performance using TP and SPEC workloads
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Improving datapath utilization of programmable DSP with composite functional units
inferred← citeshttps://doi.org/10.1109/isscc.2018.8310168openalex-snapshot
50 Years of computer architecture: From the mainframe CPU to the domain-specific tpu and the open RISC-V instruction set
inferred← citeshttps://doi.org/10.1109/mc.2017.4451206openalex-snapshot
Reduced Instruction Set Computers Then and Now
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Architecture tradeoffs in in reduced instruction set computers: a case study
inferred← citeshttps://doi.org/10.1109/tvlsi.2023.3268108openalex-snapshot
RISC-V-Based Evaluation and Strategy Exploration of MRAM Triple-Level Hybrid Cache Systems
inferred← citeshttps://doi.org/10.1109/uksim.2009.30openalex-snapshot
Design and Implementation of a 64-bit RISC Processor Using VHDL
inferred← citeshttps://doi.org/10.1109/uksim.2009.84openalex-snapshot
Dynamic Multi-level Hierarchal Clustering Approach for Wireless Sensor Networks
inferred← citeshttps://doi.org/10.1145/143369.143410openalex-snapshot
An architectural framework for migration from CISC to higher performance platforms
inferred← citeshttps://doi.org/10.1145/151220.151224openalex-snapshot
Porting OpenVMS from VAX to Alpha AXP
inferred← citeshttps://doi.org/10.1145/191995.192017openalex-snapshot
Characterization of alpha AXP performance using TP and SPEC workloads
inferred← citeshttps://doi.org/10.1145/192007.192017openalex-snapshot
Characterization of alpha AXP performance using TP and SPEC workloads
inferred← citeshttps://doi.org/10.1145/242223.242271openalex-snapshot
Strategic directions in computer architecture
inferred← citeshttps://doi.org/10.1145/248156.248164openalex-snapshot
Analysis of techniques to improve protocol processing latency
inferred← citeshttps://doi.org/10.1145/248157.248164openalex-snapshot
Analysis of techniques to improve protocol processing latency
inferred← citeshttps://doi.org/10.1145/3282307openalex-snapshot
A new golden age for computer architecture
inferred← citeshttps://doi.org/10.1145/3538644openalex-snapshot
Fuzzing of Embedded Systems: A Survey
inferred← citeshttps://doi.org/10.1145/3756681.3756953openalex-snapshot
The Impact of Environment Configurations on the Stability of AI-Enabled Systems
inferred← citeshttps://doi.org/10.1177/1094342015584495openalex-snapshot
One-IPC high-level simulation of microthreaded many-core architectures
inferred← citeshttps://doi.org/10.14257/ijunesst.2015.8.1.37openalex-snapshot
Design and Implementation of 64-Bit RISC Processor for Industry Automation
inferred← citeshttps://doi.org/10.26634/jdp.12.1.20567openalex-snapshot
Design of RISCV processor using verilog
inferred← citeshttps://doi.org/10.30574/wjarr.2024.21.1.0017openalex-snapshot
Redefining Computing: Rise of ARM from consumer to Cloud for energy efficiency
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Relatos, mapas conceptuales y arquitectura de computadores
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Empirical and Statistical Application Modeling Using on -Chip Performance Monitors.
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The Challenges of Lecture Delivery of Arm X86, Cisc and Risc in the Teaching of Coursecsc303 (Computer Architecture) in the University of Jos, Nigeria: an Overview
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