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The effect of context switches on cache performance

https://doi.org/10.1145/106975.106982
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1109/12.40842openalex-snapshot
Evaluating associativity in CPU caches
inferredcites →https://doi.org/10.1109/2.16openalex-snapshot
The Sprite network operating system
inferredcites →https://doi.org/10.1145/106972.106985openalex-snapshot
The interaction of architecture and operating system design
inferredcites →https://doi.org/10.1145/107971.107994openalex-snapshot
MTOOL
inferredcites →https://doi.org/10.1145/214451.214455openalex-snapshot
Performance of the VAX-11/780 translation buffer
inferredcites →https://doi.org/10.1145/29868.32979openalex-snapshot
Footprints in the cache
inferredcites →https://doi.org/10.1145/325164.325153openalex-snapshot
Generation and analysis of very long address traces
inferredcites →https://doi.org/10.1145/325164.325162openalex-snapshot
Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers
inferredcites →https://doi.org/10.1145/356887.356892openalex-snapshot
Cache Memories
inferredcites →https://doi.org/10.1145/48012.48037openalex-snapshot
Cache performance of operating system and multiprogramming workloads
inferredcites →https://doi.org/10.1145/63404.63407openalex-snapshot
An analytical cache model
inferredcites →https://doi.org/10.1145/70082.68200openalex-snapshot
Program optimization for instruction caches
inferredcites →https://doi.org/10.1145/74850.74861openalex-snapshot
Lightweight remote procedure call
inferredcites →https://doi.org/10.1145/75108.75380openalex-snapshot
TRAPEDS: producing traces for multicomputers via execution driven simulation

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/978-1-4471-2164-0_8openalex-snapshot
Performance and Overhead Measurements
inferred← citeshttps://doi.org/10.1016/j.sysarc.2019.02.002openalex-snapshot
vSimilar: A high-adaptive VM scheduler based on the CPU pool mechanism
inferred← citeshttps://doi.org/10.1109/icpp.1996.538568openalex-snapshot
Automatic self-allocating threads (ASAT) on an SGI Challenge
inferred← citeshttps://doi.org/10.1109/ikt.2013.6620099openalex-snapshot
Hard periodic real-time task scheduling on mobile heterogeneous processor
inferred← citeshttps://doi.org/10.1109/ipdps.2008.4536361openalex-snapshot
Effect of context aware scheduler on TLB
inferred← citeshttps://doi.org/10.1109/ispass.2001.990679openalex-snapshot
The effects of context switching on branch predictor performance
inferred← citeshttps://doi.org/10.1145/123465.123472openalex-snapshot
The effect of real data cache behavior on the performance of a microarchitecture that supports dynamic scheduling
inferred← citeshttps://doi.org/10.1145/168619.168629openalex-snapshot
The impact of operating system structure on memory system performance
inferred← citeshttps://doi.org/10.14393/ufu.di.2012.279openalex-snapshot
Estudo exploratório sobre fontes de os jitter no kernel linux
inferred← citeshttps://doi.org/10.18255/1818-1015-2018-2-165-173openalex-snapshot
Measuring Overhead of Concurrency and Virtual Memory
inferred← citeshttps://doi.org/10.24124/2007/bpgub463openalex-snapshot
Fair and efficient CPU scheduling algorithms.
inferred← citeshttps://doi.org/10.4995/thesis/10251/55328openalex-snapshot
Utilización de memorias cache con bloqueo en sistemas de tiempo real.
inferred← citeshttps://doi.org/10.5821/dissertation-2117-96039openalex-snapshot
Hardware thread scheduling algorithms for single-ISA asymmetric CMPs
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