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A fault-tolerant NoC scheme using bidirectional channel

https://doi.org/10.1145/2024724.2024929

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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1109/2.976921openalex-snapshot

Networks on chips: a new SoC paradigm

inferredcites →https://doi.org/10.1109/71.877831openalex-snapshot

The odd-even turn model for adaptive routing

inferredcites →https://doi.org/10.1109/iccad.1999.810665openalex-snapshot

Fault modeling and simulation for crosstalk in system-on-chip interconnects

inferredcites →https://doi.org/10.1109/nocs.2009.5071476openalex-snapshot

BiNoC: A bidirectional NoC architecture with dynamic self-reconfigurable channel

inferredcites →https://doi.org/10.1109/nocs.2010.10openalex-snapshot

Evaluating Bufferless Flow Control for On-chip Networks

inferredcites →https://doi.org/10.1109/pact.2009.41openalex-snapshot

Oblivious Routing in On-Chip Bandwidth-Adaptive Networks

inferredcites →https://doi.org/10.1109/tcad.2010.2048399openalex-snapshot

Fault Tolerant Network on Chip Switching With Graceful Performance Degradation

inferredcites →https://doi.org/10.1145/1391469.1391584openalex-snapshot

A reconfigurable routing algorithm for a fault-tolerant 2D-Mesh Network-on-Chip

inferredcites →https://doi.org/10.5555/1874620.1874628openalex-snapshot

A highly resilient routing algorithm for fault-tolerant NoCs

inferredcites →https://doi.org/10.5555/339492.340030openalex-snapshot

Fault modeling and simulation for crosstalk in system-on-chip interconnects

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

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Reliable and Adaptive Routing Algorithms for 2D and 3D Networks-on-Chip

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Probabilistic Verification for Reliable Network-on-Chip System Design

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Hierarchical Agents Based Fault-Tolerant and Congestion-Aware Routing for NoC

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3D Bidirectional-Channel Routing Algorithm for Network-Based Many-Core Embedded Systems

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Faulty Node Detection and Correction of Route in Network-On-Chip (NoC)

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A Light-weight fault-tolerant routing algorithm tolerating faulty links and routers

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Reliability-aware mapping for various NoC topologies and routing algorithms under performance constraints

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Fault-tolerant adaptive routing under an unconstrained set of node and link failures for many-core systems-on-chip

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Tolerating transient illegal turn faults in NoCs

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Abacus turn model-based routing for NoC interconnects with switch or link failures

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Generation and Performance Evaluation of Reconfigurable Fault Tolerant Routing Algorithm for 2D-Mesh NoC

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MD: Minimal path-based fault-tolerant routing in on-Chip Networks

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Fault-tolerant method with distributed monitoring and management technique for 3D stacked meshes

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TARAS: A topology agnostic routing algorithm using segmentation strategy for 3D NoC

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Enhanced fault-tolerant Network-on-Chip architecture using hierarchical agents

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Designing a High Performance and Reliable Networks-on-Chip Using Network Interface Assisted Routing Strategy

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MAFA: Adaptive Fault-Tolerant Routing Algorithm for Networks-on-Chip

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An Effective Routing Algorithm to Avoid Unnecessary Link Abandon in 2D Mesh NoCs

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QORE: A fault tolerant network-on-chip architecture with power-efficient quad-function channel (QFC) buffers

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FSA: An Efficient Fault-tolerant Systolic Array-based DNN Accelerator Architecture

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Evaluation of 3D & 4D Two Layer Mesh NoC for Fault Tolerance over Combinations of Vertical Channel

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LBDR3D: Fault tolerant routing scheme for 3D NoCs

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A spare router based reliable Network-on-Chip design

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A spare link based reliable Network-on-Chip design

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Towards an Effective Utilization of Partially Defected Interconnections in 2D Mesh NoCs

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FMEA-based analysis of a Network-on-Chip for mixed-critical systems

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High Performance Fault-Tolerant Routing Algorithm for NoC-Based Many-Core Systems

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Adaptive and reconfigurable fault-tolerant routing method for 2D Networks-on-Chip

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Online reconfigurable routing method for handling link failures in NoC-based MPSoCs

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Enabling NoC Performance Improvement Using a Fault Tolerance Mechanism

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MAZENOC: Novel approach for fault-tolerant NOC routing

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Novel time-multiplexing bidirectional on-chip network

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Runtime Packet-Dropping Detection of Faulty Nodes in Network-on-Chip

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Towards Maximum Utilization of Remained Bandwidth in Defected NoC Links

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An Energy-Efficient NoC Router with Adaptive Fault-Tolerance Using Channel Slicing and On-Demand TMR

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Dynamic error mitigation in NoCs using intelligent prediction techniques

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Conception d'un micro-réseau intégré NOC tolérant les fautes multiples statiques et dynamiques

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