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MAFA: Adaptive Fault-Tolerant Routing Algorithm for Networks-on-Chip

https://doi.org/10.1109/dsd.2012.82

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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

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Dynamic power management for power optimization of interconnection networks using on/off links

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DyXY - a proximity congestion-aware deadlock-free dynamic routing method for network on chip

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Trade offs in the design of a router with both guaranteed and best-effort services for networks on chip

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A highly resilient routing algorithm for fault-tolerant NoCs

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An efficent dynamic multicast routing protocol for distributing traffic in NOCs

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CATRA- congestion aware trapezoid-based routing algorithm for on-chip networks

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Fault modeling and simulation for crosstalk in system-on-chip interconnects

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Fault-tolerant wormhole routing algorithms in meshes in the presence of concave faults

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The Turn Model for Adaptive Routing

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A Lightweight Fault-Tolerant Mechanism for Network-on-Chip

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A fault-tolerant and deadlock-free routing protocol in 2D meshes based on odd-even turn model

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Agent-based on-chip network using efficient selection method

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DyXY

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A reconfigurable routing algorithm for a fault-tolerant 2D-Mesh Network-on-Chip

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The turn model for adaptive routing

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Vicis

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Optimal memory controller placement for chip multiprocessor

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Adaptive Input-Output Selection Based On-Chip Router Architecture

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A highly resilient routing algorithm for fault-tolerant NoCs

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An efficent dynamic multicast routing protocol for distributing traffic in NOCs

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CATRA- congestion aware trapezoid-based routing algorithm for on-chip networks

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Fault modeling and simulation for crosstalk in system-on-chip interconnects

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Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

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S2DIO: an extended scalable 2D mesh network-on-chip routing reconfiguration for efficient bypass of link failures

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Designs of low insertion loss optical router and reliable routing for 3D optical network-on-chip

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Graceful deadlock-free fault-tolerant routing algorithm for 3D Network-on-Chip architectures

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Fault-tolerant adaptive routing under an unconstrained set of node and link failures for many-core systems-on-chip

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Scenario preprocessing approach for the reconfiguration of fault-tolerant NoC-based MPSoCs

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NoC routing protocols – objective-based classification

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MD: Minimal path-based fault-tolerant routing in on-Chip Networks

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Fault Tolerant Deadlock-Free Adaptive Routing Algorithms for Hexagonal Networks-on-Chip

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FTNoCSim: A new Simulation platform for Evaluating Network-on-Chip Reliability

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Optimized Q-learning model for distributing traffic in on-Chip Networks

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Bi-Objective Cost Function for Adaptive Routing in Network-on-Chip

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