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Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1109/hoti.2009.16openalex-snapshot
Performance Measurement of an Integrated NIC Architecture with 10GbE
inferredcites →https://doi.org/10.1109/hpca.2009.4798237openalex-snapshot
Design and implementation of software-managed caches for multicores with local memory
inferredcites →https://doi.org/10.1109/hpca.2010.5416655openalex-snapshot
Understanding how off-chip memory bandwidth partitioning in Chip Multiprocessors affects system performance
inferredcites →https://doi.org/10.1109/hpca.2011.5749751openalex-snapshot
Architectural framework for supporting operating system survivability
inferredcites →https://doi.org/10.1109/iccd.2000.878316openalex-snapshot
A multi-level memory system architecture for high performance DSP applications
inferredcites →https://doi.org/10.1109/iccd.2009.5413123openalex-snapshot
Accelerating mobile augmented reality on a handheld platform
inferredcites →https://doi.org/10.1109/iccd11805.2006openalex-snapshot
2006 International Conference on Computer Design
inferredcites →https://doi.org/10.1109/iiswc.2009.5306788openalex-snapshot
Performance characterization and optimization of mobile augmented reality on handheld platforms
inferredcites →https://doi.org/10.1109/mm.2006.41openalex-snapshot
Synergistic Processing in Cell's Multicore Architecture
inferredcites →https://doi.org/10.1109/pact.2009.31openalex-snapshot
Architecture Support for Improving Bulk Memory Copying and Initialization Performance
inferredcites →https://doi.org/10.1145/1168857.1168884openalex-snapshot
Comprehensively and efficiently protecting the heap
inferredcites →https://doi.org/10.1145/1168857.1168894openalex-snapshot
Software-based instruction caching for embedded processors
inferredcites →https://doi.org/10.1145/1168857.1168897openalex-snapshot
Integrated network interfaces for high-bandwidth TCP/IP
inferredcites →https://doi.org/10.1145/1168917.1168897openalex-snapshot
Integrated network interfaces for high-bandwidth TCP/IP
inferredcites →https://doi.org/10.1145/1168918.1168884openalex-snapshot
Comprehensively and efficiently protecting the heap
inferredcites →https://doi.org/10.1145/1254766.1254809openalex-snapshot
Compiler-managed partitioned data caches for low power
inferredcites →https://doi.org/10.1145/1254882.1254886openalex-snapshot
QoS policies and architecture for cache/memory in CMP platforms
inferredcites →https://doi.org/10.1145/1269899.1254886openalex-snapshot
QoS policies and architecture for cache/memory in CMP platforms
inferredcites →https://doi.org/10.1145/1403375.1403666openalex-snapshot
Instruction cache energy saving through compiler way-placement
inferredcites →https://doi.org/10.1145/329166.329185openalex-snapshot
A reconfigurable multi-function computing cache architecture
inferredcites →https://doi.org/10.1145/337292.337523openalex-snapshot
Application-specific memory management for embedded systems using software-controlled caches
inferredcites →https://doi.org/10.1145/339647.339685openalex-snapshot
Reconfigurable caches and their application to media processing
inferredcites →https://doi.org/10.1145/342001.339685openalex-snapshot
Reconfigurable caches and their application to media processing
inferredcites →https://doi.org/10.1145/951710.951739openalex-snapshot
A low-power accelerator for the SPHINX 3 speech recognition system
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1109/asianhost.2016.7835559openalex-snapshot
Enhancing noise sensitivity of embedded SRAMs for robust true random number generation in SoCs
inferred← citeshttps://doi.org/10.1109/aspdac.2012.6164927openalex-snapshot
Accelerator-rich architectures: Implications, opportunities and challenges
inferred← citeshttps://doi.org/10.1109/euc.2014.27openalex-snapshot
A HLS-Based Toolflow to Design Next-Generation Heterogeneous Many-Core Platforms with Shared Memory
inferred← citeshttps://doi.org/10.1109/isca.2014.6853196openalex-snapshot
Aladdin: A pre-RTL, power-performance accelerator simulator enabling large design space exploration of customized architectures
inferred← citeshttps://doi.org/10.1109/isca.2014.6853239openalex-snapshot
WebCore: Architectural support for mobile Web browsing
inferred← citeshttps://doi.org/10.1109/isca.2018.00027openalex-snapshot
A Case for Richer Cross-Layer Abstractions: Bridging the Semantic Gap with Expressive Memory
inferred← citeshttps://doi.org/10.1109/jproc.2018.2876372openalex-snapshot
Customizable Computing—From Single Chip to Datacenters
inferred← citeshttps://doi.org/10.1109/micro.2016.7783751openalex-snapshot
Co-designing accelerators and SoC interfaces using gem5-Aladdin
inferred← citeshttps://doi.org/10.1109/mm.2015.50openalex-snapshot
The Aladdin Approach to Accelerator Design and Modeling
inferred← citeshttps://doi.org/10.1109/tc.2014.2360522openalex-snapshot
Architecture Support for Tightly-Coupled Multi-Core Clusters with Shared-Memory HW Accelerators
inferred← citeshttps://doi.org/10.1109/tvlsi.2012.2236689openalex-snapshot
Way Stealing: A Unified Data Cache and Architecturally Visible Storage for Instruction Set Extensions
inferred← citeshttps://doi.org/10.1145/1995896.1995940openalex-snapshot
Cost-effectively offering private buffers in SoCs and CMPs
inferred← citeshttps://doi.org/10.1145/2513683.2513688openalex-snapshot
Energy and performance exploration of accelerator coherency port using Xilinx ZYNQ
inferred← citeshttps://doi.org/10.1145/2744769.2744879openalex-snapshot
On-chip interconnection network for accelerator-rich architectures
inferred← citeshttps://doi.org/10.1145/2925426.2926258openalex-snapshot
Exploiting Private Local Memories to Reduce the Opportunity Cost of Accelerator Integration
inferred← citeshttps://doi.org/10.1145/2968455.2968509openalex-snapshot
Handling large data sets for high-performance embedded applications in heterogeneous systems-on-chip
inferred← citeshttps://doi.org/10.1145/3041024openalex-snapshot
Optimizing General-Purpose CPUs for Energy-Efficient Mobile Web Computing
inferred← citeshttps://doi.org/10.1145/3725843.3756066openalex-snapshot
PolymorPIC: Embedding Polymorphic Processing-in-Cache in RISC-V based Processor for Full-stack Efficient AI Inference
inferred← citeshttps://doi.org/10.1145/3730582openalex-snapshot
DCMA: Accelerating Parallel DMA Transfers with a Multi-Port Direct Cached Memory Access in a Massive-Parallel Vector Processor
inferred← citeshttps://doi.org/10.2200/s00650ed1v01y201505cac033openalex-snapshot
Customizable Computing
inferred← citeshttps://doi.org/10.2200/s01015ed1v01y202005cac052openalex-snapshot
Data Orchestration in Deep Learning Accelerators
inferred← citeshttps://doi.org/10.23919/date.2019.8715129openalex-snapshot
Queue Based Memory Management Unit for Heterogeneous MPSoCs
inferred← citeshttps://doi.org/10.7873/date.2014.038openalex-snapshot
A tightly-coupled hardware controller to improve scalability and programmability of shared-memory heterogeneous clusters
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