On the public citation graph
Co-designing accelerators and SoC interfaces using gem5-Aladdin
0 signed · 145 inferred · view as graph
Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.
Is this your work? Sign in with ORCID and put your name on the
claims that are yours.
Reference health. See whether every reference in this work resolves to a
known work and none has been retracted — and get a dated CiteStamped
badge you can embed.
What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1109/fpl.2014.6927432openalex-snapshot
Automatic high-level synthesis of multi-threaded hardware accelerators
inferredcites →https://doi.org/10.1109/hpca.2013.6522332openalex-snapshot
Reducing GPU offload latency via fine-grained CPU-GPU synchronization
inferredcites →https://doi.org/10.1109/hpca.2014.6835965openalex-snapshot
Supporting x86-64 address translation for 100s of GPU lanes
inferredcites →https://doi.org/10.1109/hpca.2015.7056040openalex-snapshot
NDA: Near-DRAM acceleration architecture leveraging commodity DRAM devices and standard memory modules
inferredcites →https://doi.org/10.1109/iccad.2014.7001431openalex-snapshot
Multithreaded pipeline synthesis for data-parallel kernels
inferredcites →https://doi.org/10.1109/iccad.2015.7372595openalex-snapshot
PARADE: A cycle-accurate full-system simulation Platform for Accelerator-Rich Architectural Design and Exploration
inferredcites →https://doi.org/10.1109/iccd.2014.6974665openalex-snapshot
Multi-accelerator system development with the ShrinkFit acceleration framework
inferredcites →https://doi.org/10.1109/iiswc.2014.6983050openalex-snapshot
MachSuite: Benchmarks for accelerator design and customized architectures
inferredcites →https://doi.org/10.1109/isca.2014.6853196openalex-snapshot
Aladdin: A pre-RTL, power-performance accelerator simulator enabling large design space exploration of customized architectures
inferredcites →https://doi.org/10.1109/isca.2016.25openalex-snapshot
ASIC Clouds: Specializing the Datacenter
inferredcites →https://doi.org/10.1109/isca.2016.32openalex-snapshot
Minerva: Enabling Low-Power, Highly-Accurate Deep Neural Network Accelerators
inferredcites →https://doi.org/10.1109/ispass.2013.6557175openalex-snapshot
ISA-independent workload characterization and its implications for specialized architectures
inferredcites →https://doi.org/10.1109/ispass.2014.6844457openalex-snapshot
Sources of error in full-system simulation
inferredcites →https://doi.org/10.1109/isscc.2016.7418007openalex-snapshot
14.5 Eyeriss: An energy-efficient reconfigurable accelerator for deep convolutional neural networks
inferredcites →https://doi.org/10.1109/lca.2014.2299539openalex-snapshot
gem5-gpu: A Heterogeneous CPU-GPU Simulator
inferredcites →https://doi.org/10.1109/micro.2010.36openalex-snapshot
Single-Chip Heterogeneous Computing: Does the Future Include Custom Logic, FPGAs, and GPGPUs?
inferredcites →https://doi.org/10.1109/micro.2012.48openalex-snapshot
Neural Acceleration for General-Purpose Approximate Programs
inferredcites →https://doi.org/10.1109/micro.2014.60openalex-snapshot
Short-Circuiting Memory Traffic in Handheld Platforms
inferredcites →https://doi.org/10.1109/mm.2006.49openalex-snapshot
Cell Multiprocessor Communication Network: Built for Speed
inferredcites →https://doi.org/10.1145/1815961.1815968openalex-snapshot
Understanding sources of inefficiency in general-purpose chips
inferredcites →https://doi.org/10.1145/232973.232983openalex-snapshot
Memory bandwidth limitations of future microprocessors
inferredcites →https://doi.org/10.1145/2370816.2370872openalex-snapshot
Hardware acceleration in the IBM PowerEN processor
inferredcites →https://doi.org/10.1145/2435264.2435266openalex-snapshot
Building zynq® accelerators with Vivado® high level synthesis
inferredcites →https://doi.org/10.1145/2485922.2485926openalex-snapshot
Thin servers with smart pipes
inferredcites →https://doi.org/10.1145/2485922.2485944openalex-snapshot
Navigating big data with high-throughput, energy-efficient data partitioning
inferredcites →https://doi.org/10.1145/2540708.2540747openalex-snapshot
Heterogeneous system coherence for integrated CPU-GPU systems
inferredcites →https://doi.org/10.1145/2541940.2541942openalex-snapshot
Architectural support for address translation on GPUs
inferredcites →https://doi.org/10.1147/jrd.2013.2280090openalex-snapshot
IBM POWER7+ processor on-chip accelerators for cryptography and active memory expansion
inferredcites →https://doi.org/10.1147/rd.515.0559openalex-snapshot
Cell Broadband Engine Architecture and its first implementation—A performance view
inferredcites →https://doi.org/10.2200/s00677ed1v01y201511cac034openalex-snapshot
Research Infrastructures for Hardware Accelerators
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-3-030-55704-1_3openalex-snapshot
Fault Injection Framework Using Virtual Platforms
inferred← citeshttps://doi.org/10.1007/978-3-030-78713-4_4openalex-snapshot
A Hierarchical Task Scheduler for Heterogeneous Computing
inferred← citeshttps://doi.org/10.1007/978-3-031-01764-3_10openalex-snapshot
Consistency and Coherence for Heterogeneous Systems
inferred← citeshttps://doi.org/10.1007/978-3-031-16344-9_15openalex-snapshot
DoS Attack Models and Mitigation Frameworks for NoC-Based SoCs
inferred← citeshttps://doi.org/10.1007/978-3-031-32041-5_1openalex-snapshot
CPU Architecture Modelling and Co-design
inferred← citeshttps://doi.org/10.1007/978-3-031-46077-7_7openalex-snapshot
Characterization of a Coherent Hardware Accelerator Framework for SoCs
inferred← citeshttps://doi.org/10.1007/978-981-95-8411-6_50openalex-snapshot
HManyCore-Sim: Heterogeneous Simulator for Deeply Fused Many-Core Processor
inferred← citeshttps://doi.org/10.1007/978-981-97-0859-8_1openalex-snapshot
CSDSE: Apply Cooperative Search to Solve the Exploration-Exploitation Dilemma of Design Space Exploration
inferred← citeshttps://doi.org/10.1007/s11227-020-03495-5openalex-snapshot
Performance and power consumption analysis of Arm Scalable Vector Extension
inferred← citeshttps://doi.org/10.1016/j.sysarc.2024.103211openalex-snapshot
Expanding hardware accelerator system design space exploration with gem5-SALAMv2
inferred← citeshttps://doi.org/10.1038/s44287-025-00187-1openalex-snapshot
Deep learning software stacks for analogue in-memory computing-based accelerators
inferred← citeshttps://doi.org/10.1098/rsta.2019.0061openalex-snapshot
The future of computing beyond Moore’s Law
inferred← citeshttps://doi.org/10.1109/access.2022.3154014openalex-snapshot
Modeling and Simulation of System Bus and Memory Collisions in Heterogeneous SoCs
inferred← citeshttps://doi.org/10.1109/access.2022.3204664openalex-snapshot
Architecture and Application Co-Design for Beyond-FPGA Reconfigurable Acceleration Devices
inferred← citeshttps://doi.org/10.1109/access.2024.3352924openalex-snapshot
NDPmulator: Enabling Full-System Simulation for Near-Data Accelerators From Caches to DRAM
inferred← citeshttps://doi.org/10.1109/access.2024.3365632openalex-snapshot
Domain-Specific STT-MRAM-Based In-Memory Computing: A Survey
inferred← citeshttps://doi.org/10.1109/asap.2019.00013openalex-snapshot
Understanding Performance Gains of Accelerator-Rich Architectures
inferred← citeshttps://doi.org/10.1109/asap65064.2025.00015openalex-snapshot
PRDSE: A Prior-Driven Design Space Exploration Method
inferred← citeshttps://doi.org/10.1109/asicon58565.2023.10396658openalex-snapshot
Coupled Data Prefetch and Cache Partitioning Scheme for CPU-Accelerator System
inferred← citeshttps://doi.org/10.1109/coolchips52128.2021.9410320openalex-snapshot
Power/Performance/Area Evaluations for Next-Generation HPC Processors using the A64FX Chip
inferred← citeshttps://doi.org/10.1109/cvpr52734.2025.02806openalex-snapshot
DeepCompress-ViT: Rethinking Model Compression to Enhance Efficiency of Vision Transformers at the Edge
inferred← citeshttps://doi.org/10.1109/dac.2018.8465855openalex-snapshot
Extensive Evaluation of Programming Models and ISAs Impact on Multicore So Error Reliability
inferred← citeshttps://doi.org/10.1109/dac.2018.8465904openalex-snapshot
Locality Aware Memory Assignment and Tiling
inferred← citeshttps://doi.org/10.1109/dac.2018.8465921openalex-snapshot
Active Forwarding: Eliminate IOMMU Address Translation for Accelerator-rich Architectures
inferred← citeshttps://doi.org/10.1109/hpca.2017.19openalex-snapshot
Supporting Address Translation for Accelerator-Centric Architectures
inferred← citeshttps://doi.org/10.1109/hpca51647.2021.00041openalex-snapshot
EXMA: A Genomics Accelerator for Exact-Matching
inferred← citeshttps://doi.org/10.1109/hpca53966.2022.00052openalex-snapshot
Compiler-Driven Simulation of Reconfigurable Hardware Accelerators
inferred← citeshttps://doi.org/10.1109/hpca57654.2024.00047openalex-snapshot
Gem5-MARVEL: Microarchitecture-Level Resilience Analysis of Heterogeneous SoC Architectures
inferred← citeshttps://doi.org/10.1109/hpca68181.2026.11408541openalex-snapshot
Area Bloating and the Future of Specialization
inferred← citeshttps://doi.org/10.1109/iccad66269.2025.11240659openalex-snapshot
Rhea: a Framework for Fast Design and Validation of RTL Cache-Coherent Memory Subsystems
inferred← citeshttps://doi.org/10.1109/iccd46524.2019.00024openalex-snapshot
Compiler-Assisted Selection of Hardware Acceleration Candidates from Application Source Code
inferred← citeshttps://doi.org/10.1109/iccd46524.2019.00052openalex-snapshot
Flexible NTT Accelerators for RLWE Lattice-Based Cryptography
inferred← citeshttps://doi.org/10.1109/iccd46524.2019.00077openalex-snapshot
A High-Performance Processing-in-Memory Accelerator for Inline Data Deduplication
inferred← citeshttps://doi.org/10.1109/icce-berlin67488.2025.11277935openalex-snapshot
Extending gem5 with a Developer-Centric IDE for SoC Architecture Simulation
inferred← citeshttps://doi.org/10.1109/iccsse59359.2023.10245050openalex-snapshot
Exploring the Architecture of Multiple GEMM Accelerators in Heterogeneous Systems
inferred← citeshttps://doi.org/10.1109/icsess58500.2023.10293121openalex-snapshot
Parallel Optimization and Hardware Customization for Fast Fourier Transform
inferred← citeshttps://doi.org/10.1109/iiswc.2016.7581272openalex-snapshot
SPEC-AX and PARSEC-AX: extracting accelerator benchmarks from microprocessor benchmarks
inferred← citeshttps://doi.org/10.1109/iiswc50251.2020.00011openalex-snapshot
HETSIM: Simulating Large-Scale Heterogeneous Systems using a Trace-driven, Synchronization and Dependency-Aware Framework
inferred← citeshttps://doi.org/10.1109/iiswc50251.2020.00034openalex-snapshot
Reconfigurable Accelerator Compute Hierarchy: A Case Study using Content-Based Image Retrieval
inferred← citeshttps://doi.org/10.1109/iiswc59245.2023.00038openalex-snapshot
ERAS: A Flexible and Scalable Framework for Seamless Integration of RTL Models with Structural Simulation Toolkit
inferred← citeshttps://doi.org/10.1109/ipdpsw59300.2023.00016openalex-snapshot
CEDR-API: Productive, Performant Programming of Domain-Specific Embedded Systems
inferred← citeshttps://doi.org/10.1109/ipdpsw63119.2024.00073openalex-snapshot
A Comparative Study on Simulation Frameworks for AI Accelerator Evaluation
inferred← citeshttps://doi.org/10.1109/isca.2018.00038openalex-snapshot
Scaling Datacenter Accelerators with Compute-Reuse Architectures
inferred← citeshttps://doi.org/10.1109/isca45697.2020.00046openalex-snapshot
Mocktails: Capturing the Memory Behaviour of Proprietary Mobile Architectures
inferred← citeshttps://doi.org/10.1109/isca52012.2021.00086openalex-snapshot
HASCO: Towards Agile HArdware and Software CO-design for Tensor Computation
inferred← citeshttps://doi.org/10.1109/iscas48785.2022.9937422openalex-snapshot
NNASIM: An Efficient Event-Driven Simulator for DNN Accelerators with Accurate Timing and Area Models
inferred← citeshttps://doi.org/10.1109/ispass48437.2020.00029openalex-snapshot
MosaicSim: A Lightweight, Modular Simulator for Heterogeneous Systems
inferred← citeshttps://doi.org/10.1109/ispass51385.2021.00042openalex-snapshot
Architecture-Level Energy Estimation for Heterogeneous Computing Systems
inferred← citeshttps://doi.org/10.1109/ispass55109.2022.00042openalex-snapshot
Bifrost: End-to-End Evaluation and optimization of Reconfigurable DNN Accelerators
inferred← citeshttps://doi.org/10.1109/itc-cscc62988.2024.10628263openalex-snapshot
Thermal Simulation of ML Applications on a Commercial DRAM-Based PIM
inferred← citeshttps://doi.org/10.1109/lca.2019.2893932openalex-snapshot
Scalable LLVM-Based Accelerator Modeling in gem5
inferred← citeshttps://doi.org/10.1109/lca.2019.2910521openalex-snapshot
Determining Optimal Coherency Interface for Many-Accelerator SoCs Using Bayesian Optimization
inferred← citeshttps://doi.org/10.1109/lca.2023.3329443openalex-snapshot
gem5-accel: A Pre-RTL Simulation Toolchain for Accelerator Architecture Validation
inferred← citeshttps://doi.org/10.1109/les.2021.3050253openalex-snapshot
Quant-PIM: An Energy-Efficient Processing-in-Memory Accelerator for Layerwise Quantized Neural Networks
inferred← citeshttps://doi.org/10.1109/mcsoc.2019.00045openalex-snapshot
Designing Application-Specific Heterogeneous Architectures from Performance Models
inferred← citeshttps://doi.org/10.1109/micro50266.2020.00047openalex-snapshot
gem5-SALAM: A System Architecture for LLVM-based Accelerator Modeling
inferred← citeshttps://doi.org/10.1109/micro50266.2020.00058openalex-snapshot
ConfuciuX: Autonomous Hardware Resource Assignment for DNN Accelerators using Reinforcement Learning
inferred← citeshttps://doi.org/10.1109/micro56248.2022.00094openalex-snapshot
DeepBurning-SEG: Generating DNN Accelerators of Segment-Grained Pipeline Architecture
inferred← citeshttps://doi.org/10.1109/mm.2018.2877288openalex-snapshot
Accelerators and Coherence: An SoC Perspective
inferred← citeshttps://doi.org/10.1109/mwscas.2017.8053070openalex-snapshot
Methods and infrastructure in the era of accelerator-centric architectures
inferred← citeshttps://doi.org/10.1109/nocs.2018.8512153openalex-snapshot
NoC-Based Support of Heterogeneous Cache-Coherence Models for Accelerators
inferred← citeshttps://doi.org/10.1109/pdp50117.2020.00053openalex-snapshot
Partition Pruning: Parallelization-Aware Pruning for Dense Neural Networks
inferred← citeshttps://doi.org/10.1109/recosoc48741.2019.9034940openalex-snapshot
Data Transfer Modeling and Optimization in Reconfigurable Multi-Accelerator Systems
inferred← citeshttps://doi.org/10.1109/rsp51120.2020.9244859openalex-snapshot
A combined fast/cycle accurate simulation tool for reconfigurable accelerator evaluation: application to distributed data management
inferred← citeshttps://doi.org/10.1109/rtcsa.2018.00021openalex-snapshot
Phase-Based Profiling and Performance Prediction with Timing Approximate Simulators
inferred← citeshttps://doi.org/10.1109/sbac-pad53543.2021.00015openalex-snapshot
SECDA: Efficient Hardware/Software Co-Design of FPGA-based DNN Accelerators for Edge Inference
inferred← citeshttps://doi.org/10.1109/socc.2018.8618516openalex-snapshot
Co-Optimizing CPUs and Accelerators in Constrained Systems
inferred← citeshttps://doi.org/10.1109/tc.2021.3071507openalex-snapshot
Plasticity-on-Chip Design: Exploiting Self-Similarity for Data Communications
inferred← citeshttps://doi.org/10.1109/tc.2022.3169434openalex-snapshot
Sky-Sorter: A Processing-in-Memory Architecture for Large-Scale Sorting
inferred← citeshttps://doi.org/10.1109/tc.2023.3347675openalex-snapshot
Gem5Tune: A Parameter Auto-Tuning Framework for Gem5 Simulator to Reduce Errors
inferred← citeshttps://doi.org/10.1109/tcad.2019.2925377openalex-snapshot
MemFlow: Memory-Driven Data Scheduling With Datapath Co-Design in Accelerators for Large-Scale Inference Applications
inferred← citeshttps://doi.org/10.1109/tcad.2022.3197535openalex-snapshot
CASPHAr: Cache-Managed Accelerator Staging and Pipelining in Heterogeneous System Architectures
inferred← citeshttps://doi.org/10.1109/tetc.2021.3049826openalex-snapshot
Securing an Accelerator-rich System from Flooding-based Denial-of-Service Attacks
inferred← citeshttps://doi.org/10.1109/tmscs.2018.2879601openalex-snapshot
A Novel, Simulator for Heterogeneous Cloud Systems that Incorporate Custom Hardware Accelerators
inferred← citeshttps://doi.org/10.1109/tpds.2021.3056045openalex-snapshot
Hardware Accelerator Integration Tradeoffs for High-Performance Computing: A Case Study of GEMM Acceleration in N-Body Methods
inferred← citeshttps://doi.org/10.1111/cgf.70212openalex-snapshot
Arches: A Cycle‐Level Hardware Simulation Framework for Exploring Massively Parallel Ray Tracing Architectures
inferred← citeshttps://doi.org/10.1145/3370748.3406564openalex-snapshot
A comprehensive methodology to determine optimal coherence interfaces for many-accelerator SoCs
inferred← citeshttps://doi.org/10.1145/3378164openalex-snapshot
Synthesis of Flexible Accelerators for Early Adoption of Ring-LWE Post-quantum Cryptography
inferred← citeshttps://doi.org/10.1145/3400302.3415751openalex-snapshot
A simulator and compiler framework for agile hardware-software co-design evaluation and exploration
inferred← citeshttps://doi.org/10.1145/3466752.3480065openalex-snapshot
Cohmeleon: Learning-Based Orchestration of Accelerator Coherence in Heterogeneous SoCs
inferred← citeshttps://doi.org/10.1145/3466752.3480094openalex-snapshot
NOVIA: A Framework for Discovering Non-Conventional Inline Accelerators
inferred← citeshttps://doi.org/10.1145/3529257openalex-snapshot
CEDR: A Compiler-integrated, Extensible DSSoC Runtime
inferred← citeshttps://doi.org/10.1145/3544016openalex-snapshot
FARSI: An Early-stage Design Space Exploration Framework to Tame the Domain-specific System-on-chip Complexity
inferred← citeshttps://doi.org/10.1145/3545177openalex-snapshot
ACDSE: A Design Space Exploration Method for CNN Accelerator based on Adaptive Compression Mechanism
inferred← citeshttps://doi.org/10.1145/3579371.3589055openalex-snapshot
K-D Bonsai: ISA-Extensions to Compress K-D Trees for Autonomous Driving Tasks
inferred← citeshttps://doi.org/10.1145/3650200.3656592openalex-snapshot
LCM: LLM-focused Hybrid SPM-cache Architecture with Cache Management for Multi-Core AI Accelerators
inferred← citeshttps://doi.org/10.1145/3656019.3676896openalex-snapshot
Mozart: Taming Taxes and Composing Accelerators with Shared-Memory
inferred← citeshttps://doi.org/10.1145/3661997openalex-snapshot
gem5-NVDLA: A Simulation Framework for Compiling, Scheduling, and Architecture Evaluation on AI System-on-Chips
inferred← citeshttps://doi.org/10.1145/3757742openalex-snapshot
FLASH: Deadline-Aware Flexible LLC Arbitration and Scheduling for Hardware Accelerators
inferred← citeshttps://doi.org/10.1145/3803551openalex-snapshot
Mitigating the Bandwidth Wall via Data-Streaming System–Accelerator Co-Design
inferred← citeshttps://doi.org/10.1201/9781003358817-9openalex-snapshot
The Future of Computing beyond Moore's Law
inferred← citeshttps://doi.org/10.12681/eadd/52494openalex-snapshot
Accelerating irregular applications via efficient synchronization and data access techniques
inferred← citeshttps://doi.org/10.2200/s00962ed2v01y201910cac049openalex-snapshot
A Primer on Memory Consistency and Cache Coherence, Second Edition
inferred← citeshttps://doi.org/10.23919/date69613.2026.11539409openalex-snapshot
CISim: ISA-Agnostic Custom Instruction Simulation for General-Purpose Processor
inferred← citeshttps://doi.org/10.23919/fpl.2017.8056775openalex-snapshot
PAAS: A system level simulator for heterogeneous computing architectures
inferred← citeshttps://doi.org/10.3390/electronics10050623openalex-snapshot
A System-Level Exploration of Binary Neural Network Accelerators with Monolithic 3D Based Compute-in-Memory SRAM
inferred← citeshttps://doi.org/10.3390/electronics14051032openalex-snapshot
Efficient Modeling and Usage of Scratchpad Memory for Artificial Intelligence Accelerators
inferred← citeshttps://doi.org/10.3390/electronics7040045openalex-snapshot
Design and Application Space Exploration of a Domain-Specific Accelerator System
inferred← citeshttps://doi.org/10.3390/mi15030343openalex-snapshot
Intermittent-Aware Design Exploration of Systolic Array Using Various Non-Volatile Memory: A Comparative Study
inferred← citeshttps://doi.org/10.5121/mlaij.2021.8402openalex-snapshot
A Survey of Neural Network Hardware Accelerators in Machine Learning
Editorial review for independent work. ICSAC — the Institute for Complexity
Science and Advanced Computing — runs a structured editorial panel for researchers
publishing outside journals, and publishes on CiteStamp rails. Submission is free
and goes through ORCID: icsacinstitute.org/submit.