On the public citation graph
Proceedings of the 22nd annual international symposium on Computer architecture - ISCA '95
0 signed · 58 inferred · view as graph
Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.
Is this your work? Sign in with ORCID and put your name on the
claims that are yours.
Reference health. See whether every reference in this work resolves to a
known work and none has been retracted — and get a dated CiteStamped
badge you can embed.
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-3-642-19475-7_14openalex-snapshot
CReAMS: An Embedded Multiprocessor Platform
inferred← citeshttps://doi.org/10.1007/978-3-642-19853-3_57openalex-snapshot
An Effective Conflict Management for Large Transactions in Hardware Transactional Memory System
inferred← citeshttps://doi.org/10.1007/978-3-642-19853-3_58openalex-snapshot
A Comprehensive Scheme for Contention Management in Hardware Transactional Memory
inferred← citeshttps://doi.org/10.1007/978-3-642-21599-5_13openalex-snapshot
CPU Support for Secure Executables
inferred← citeshttps://doi.org/10.1007/978-3-642-27257-8_13openalex-snapshot
Memory Encryption for Smart Cards
inferred← citeshttps://doi.org/10.1007/978-3-642-54212-1_2openalex-snapshot
Collaborative Memories in Clusters: Opportunities and Challenges
inferred← citeshttps://doi.org/10.1007/s11042-012-1252-4openalex-snapshot
Interactive multi-frame reconstruction for mobile devices
inferred← citeshttps://doi.org/10.1007/s11227-013-0999-3openalex-snapshot
HybridPlan: a capacity planning technique for projecting storage requirements in hybrid storage systems
inferred← citeshttps://doi.org/10.1007/s11432-014-5175-8openalex-snapshot
Improving multiprocessor performance with fine-grain coherence bypass
inferred← citeshttps://doi.org/10.1016/b978-0-08-100512-5.00009-7openalex-snapshot
Scalable three-dimensional optical interconnects for data centers
inferred← citeshttps://doi.org/10.1016/b978-0-12-802459-1.00002-6openalex-snapshot
Reliable and power-aware architectures
inferred← citeshttps://doi.org/10.1016/b978-0-12-818279-6.00017-7openalex-snapshot
Case study of hardware implementation
inferred← citeshttps://doi.org/10.1016/j.future.2020.03.058openalex-snapshot
Sequence-to-sequence models for workload interference prediction on batch processing datacenters
inferred← citeshttps://doi.org/10.1016/j.jss.2014.06.058openalex-snapshot
Hybrid address spaces: A methodology for implementing scalable high-level programming models on non-coherent many-core architectures
inferred← citeshttps://doi.org/10.1016/j.micpro.2015.11.004openalex-snapshot
Energy-efficient synonym data detection and consistency for virtual cache
inferred← citeshttps://doi.org/10.1016/j.simpat.2018.02.002openalex-snapshot
Simulating heterogeneous behaviours in complex systems on GPUs
inferred← citeshttps://doi.org/10.1016/j.softx.2018.03.006openalex-snapshot
libVersioningCompiler: An easy-to-use library for dynamic generation and invocation of multiple code versions
inferred← citeshttps://doi.org/10.1016/j.suscom.2017.08.005openalex-snapshot
P 2 NoC: Power- and Performance-aware NoC Architectures for Sustainable Computing
inferred← citeshttps://doi.org/10.1016/j.suscom.2017.10.015openalex-snapshot
Performance and energy metrics for multi-threaded applications on DVFS processors
inferred← citeshttps://doi.org/10.1016/j.suscom.2020.100449openalex-snapshot
Line-Coalescing DRAM Cache
inferred← citeshttps://doi.org/10.1016/j.sysarc.2015.12.003openalex-snapshot
A thermal-aware scheduling for multicore architectures
inferred← citeshttps://doi.org/10.1016/j.sysarc.2016.06.007openalex-snapshot
A compiler assisted wear leveling for morphable PCM in embedded systems
inferred← citeshttps://doi.org/10.1016/s0065-2458(03)61002-8openalex-snapshot
Efficient Architectural Design of High Performance Microprocessors
inferred← citeshttps://doi.org/10.1039/c7ta04968dopenalex-snapshot
Versatility of polyethylene glycol (PEG) in designing solid–solid phase change materials (PCMs) for thermal management and their application to innovative technologies
inferred← citeshttps://doi.org/10.1145/1061267.1061269openalex-snapshot
Efficient and flexible architectural support for dynamic monitoring
inferred← citeshttps://doi.org/10.1145/307338.300986openalex-snapshot
Tolerating late memory traps in ILP processors
inferred← citeshttps://doi.org/10.1145/329466.329486openalex-snapshot
Effective fine-grain synchronization for automatically parallelized programs using optimistic synchronization primitives
inferred← citeshttps://doi.org/10.1145/332799.332800openalex-snapshot
A high-level abstraction of shared accesses
inferred← citeshttps://doi.org/10.1145/3362033openalex-snapshot
Toward Customized Hybrid Fuel-Cell and Battery-powered Mobile Device for Individual Users
inferred← citeshttps://doi.org/10.1145/3429440openalex-snapshot
Reducing Energy in GPGPUs through Approximate Trivial Bypassing
inferred← citeshttps://doi.org/10.1145/3431803openalex-snapshot
Reliability-aware Garbage Collection for Hybrid HBM-DRAM Memories
inferred← citeshttps://doi.org/10.1145/3460087openalex-snapshot
Mix and Match: Reorganizing Tasks for Enhancing Data Locality
inferred← citeshttps://doi.org/10.1145/3590153openalex-snapshot
A Multi-tenant Key-value SSD with Secondary Index for Search Query Processing and Analysis
inferred← citeshttps://doi.org/10.1145/3639471openalex-snapshot
Bridging Software-Hardware for CXL Memory Disaggregation in Billion-Scale Nearest Neighbor Search
inferred← citeshttps://doi.org/10.1145/3641853openalex-snapshot
Tyche: An Efficient and General Prefetcher for Indirect Memory Accesses
inferred← citeshttps://doi.org/10.1145/3652024.3665509openalex-snapshot
Supporting Trusted Virtual Machines with Hardware-Based Secure Remote Memory
inferred← citeshttps://doi.org/10.1145/3669940.3707231openalex-snapshot
Using Analytical Performance/Power Model and Fine-Grained DVFS to Enhance AI Accelerator Energy Efficiency
inferred← citeshttps://doi.org/10.1145/3727200.3727226openalex-snapshot
Lovelock: Towards Smart NIC-Hosted Clusters
inferred← citeshttps://doi.org/10.1145/3732940openalex-snapshot
9Ring: A 3D-Stacked Memory-Based Accelerator for Flexible and Efficient Deep CNN Applications
inferred← citeshttps://doi.org/10.1145/3750448openalex-snapshot
RACER: Avoiding End-to-End Slowdowns in Accelerated Chip Multi-Processors
inferred← citeshttps://doi.org/10.1145/3768585openalex-snapshot
JUNO++: Optimizing ANNS and Enabling Efficient Sparse Attention in LLM via Ray Tracing Core
inferred← citeshttps://doi.org/10.1177/0037549704044326openalex-snapshot
Speeding Up Architectural Simulations for High-Performance Processors
inferred← citeshttps://doi.org/10.37099/mtu.dc.etdr/589openalex-snapshot
Mitigating the Effect of Misspeculations in Superscalar Processors
Editorial review for independent work. ICSAC — the Institute for Complexity
Science and Advanced Computing — runs a structured editorial panel for researchers
publishing outside journals, and publishes on CiteStamp rails. Submission is free
and goes through ORCID: icsacinstitute.org/submit.