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Scale-out processors
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1016/j.sse.2007.02.004openalex-snapshot
A perspective on today’s scaling challenges and possible future directions
inferredcites →https://doi.org/10.1109/arvlsi.1997.634861openalex-snapshot
An embedded DRAM for CMOS ASICs
inferredcites →https://doi.org/10.1109/ectc.2011.5898709openalex-snapshot
Die to die copper wire bonding enabling low cost 3D packaging
inferredcites →https://doi.org/10.1109/eptc.2008.4763465openalex-snapshot
Development of Fine Pitch Solder Microbumps for 3D Chip Stacking
inferredcites →https://doi.org/10.1109/hpca.2001.903254openalex-snapshot
JETTY: filtering snoops for reduced energy consumption in SMP servers
inferredcites →https://doi.org/10.1109/hpca.2009.4798250openalex-snapshot
Elastic-buffer flow control for on-chip networks
inferredcites →https://doi.org/10.1109/icicdt.2008.4567286openalex-snapshot
3D Contactless communication for IC design
inferredcites →https://doi.org/10.1109/icpp.2003.1240600openalex-snapshot
Performance and power impact of issue-width in chip-multiprocessor cores
inferredcites →https://doi.org/10.1109/iitc.2005.1499971openalex-snapshot
Wafer-level microfluidic cooling interconnects for GSI
inferredcites →https://doi.org/10.1109/isca.2008.37openalex-snapshot
Understanding and Designing New Server Architectures for Emerging Warehouse-Computing Environments
inferredcites →https://doi.org/10.1109/isscc.2007.373605openalex-snapshot
Design of the Power6 Microprocessor
inferredcites →https://doi.org/10.1109/isscc.2007.373608openalex-snapshot
An Integrated Quad-Core Opteron Processor
inferredcites →https://doi.org/10.1109/isscc.2009.4977306openalex-snapshot
A family of 45nm IA processors
inferredcites →https://doi.org/10.1109/isscc.2010.5434030openalex-snapshot
A 40nm 16-core 128-thread CMT SPARC SoC processor
inferredcites →https://doi.org/10.1109/isscc.2010.5434033openalex-snapshot
Westmere: A family of 32nm IA processors
inferredcites →https://doi.org/10.1109/isscc.2012.6176900openalex-snapshot
A compact low-power 3D I/O in 45nm CMOS
inferredcites →https://doi.org/10.1109/isvlsi.2009.27openalex-snapshot
An Analytical Model to Study Optimal Area Breakdown between Cores and Caches in a Chip Multiprocessor
inferredcites →https://doi.org/10.1109/jetcas.2012.2193837openalex-snapshot
Design and Testing Strategies for Modular 3-D-Multiprocessor Systems Using Die-Level Through Silicon Via Technology
inferredcites →https://doi.org/10.1109/jssc.1974.1050511openalex-snapshot
Design of ion-implanted MOSFET's with very small physical dimensions
inferredcites →https://doi.org/10.1109/mdt.2005.136openalex-snapshot
Demystifying 3D ICs: The Pros and Cons of Going Vertical
inferredcites →https://doi.org/10.1109/micro.2006.10openalex-snapshot
ASR: Adaptive Selective Replication for CMP Caches
inferredcites →https://doi.org/10.1109/micro.2006.18openalex-snapshot
Die Stacking (3D) Microarchitecture
inferredcites →https://doi.org/10.1109/micro.2006.31openalex-snapshot
Managing Distributed, Shared L2 Caches through OS-Level Page Allocation
inferredcites →https://doi.org/10.1109/micro.2007.30openalex-snapshot
Dynamic Warp Formation and Scheduling for Efficient GPU Control Flow
inferredcites →https://doi.org/10.1109/micro.2007.33openalex-snapshot
Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0
inferredcites →https://doi.org/10.1109/micro.2010.50openalex-snapshot
Throughput-Effective On-Chip Networks for Manycore Accelerators
inferredcites →https://doi.org/10.1109/micro.2012.25openalex-snapshot
NOC-Out: Microarchitecting a Scale-Out Processor
inferredcites →https://doi.org/10.1109/mm.2003.1196112openalex-snapshot
Web search for a planet: the google cluster architecture
inferredcites →https://doi.org/10.1109/mm.2006.79openalex-snapshot
SimFlex: Statistical Sampling of Computer System Simulation
inferredcites →https://doi.org/10.1109/mm.2007.59openalex-snapshot
Processor Design in 3D Die-Stacking Technologies
inferredcites →https://doi.org/10.1109/nocs.2012.15openalex-snapshot
CCNoC: Specializing On-Chip Interconnects for Energy Efficiency in Cache-Coherent Servers
inferredcites →https://doi.org/10.1109/pact.2005.42openalex-snapshot
Maximizing CMP throughput with mediocre cores
inferredcites →https://doi.org/10.1145/1080695.1070001openalex-snapshot
Optimizing Replication, Communication, and Capacity Allocation in CMPs
inferredcites →https://doi.org/10.1145/1088149.1088154openalex-snapshot
A NUCA substrate for flexible CMP cache sharing
inferredcites →https://doi.org/10.1145/1150019.1136509openalex-snapshot
Cooperative Caching for Chip Multiprocessors
inferredcites →https://doi.org/10.1145/1183401.1183430openalex-snapshot
Design tradeoffs for tiled CMP on-chip networks
inferredcites →https://doi.org/10.1145/1278480.1278623openalex-snapshot
Interconnects in the third dimension
inferredcites →https://doi.org/10.1145/1366230.1366261openalex-snapshot
A modular 3d processor for flexible product design and technology migration
inferredcites →https://doi.org/10.1145/1378533.1378535openalex-snapshot
Utilizing shared data in chip multiprocessors with the Nahalal architecture
inferredcites →https://doi.org/10.1145/1394608.1382148openalex-snapshot
Understanding and Designing New Server Architectures for Emerging Warehouse-Computing Environments
inferredcites →https://doi.org/10.1145/1555754.1555781openalex-snapshot
A case for bufferless routing in on-chip networks
inferredcites →https://doi.org/10.1145/1807128.1807152openalex-snapshot
Benchmarking cloud serving systems with YCSB
inferredcites →https://doi.org/10.1145/1815961.1816002openalex-snapshot
Web search using mobile cores
inferredcites →https://doi.org/10.1145/191995.192066openalex-snapshot
A study of single-chip processor/cache organizations for large numbers of transistors
inferredcites →https://doi.org/10.1145/1998582.1998590openalex-snapshot
Memory power management via dynamic voltage/frequency scaling
inferredcites →https://doi.org/10.1145/2155620.2155651openalex-snapshot
System-level integrated server architectures for scale-out datacenters
inferredcites →https://doi.org/10.1145/2382553.2382557openalex-snapshot
Quantifying the Mismatch between Emerging Scale-Out Applications and Modern Processors
inferredcites →https://doi.org/10.1145/605397.605420openalex-snapshot
An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches
inferredcites →https://doi.org/10.21236/ada632211openalex-snapshot
A Crossbar System for Multiprocessors
inferredcites →https://doi.org/10.2200/s00193ed1v01y200905cac006openalex-snapshot
The Datacenter as a Computer: An Introduction to the Design of Warehouse-Scale Machines
inferredcites →https://doi.org/10.5555/1129601.1129707openalex-snapshot
Thermal via planning for 3-D ICs
inferredcites →https://doi.org/10.5555/1413370.1413399openalex-snapshot
A novel migration-based NUCA design for chip multiprocessors
inferredcites →https://doi.org/10.5555/645988.674164openalex-snapshot
Exploring the Design Space of Future CMPs
inferredcites →https://doi.org/10.5555/956417.956568openalex-snapshot
Power-driven design of router microarchitectures in on-chip networks
inferredcites →https://doi.org/10.5555/956417.956577openalex-snapshot
Distance associativity for high-performance energy-efficient non-uniform cache architectures
inferredcites →https://doi.org/10.5555/996070.1009873openalex-snapshot
Efficient Thermal Placement of Standard Cells in 3D ICs using a Force Directed Approach
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.2139/ssrn.4192491openalex-extracted
A Fine-Grained Page Management Scheme For Hpc Manycore I/O Systems
inferred← citeshttps://doi.org/10.1002/9781119818410.ch6openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/978-3-319-10596-3_11openalex-snapshot
BDGS: A Scalable Big Data Generator Suite in Big Data Benchmarking
inferred← citeshttps://doi.org/10.1007/978-3-319-27119-4_8openalex-snapshot
A Study on Non-volatile 3D Stacked Memory for Big Data Applications
inferred← citeshttps://doi.org/10.1007/978-3-642-53974-9_5openalex-snapshot
The Implications of Diverse Applications and Scalable Data Sets in Benchmarking Big Data Systems
inferred← citeshttps://doi.org/10.1007/s00607-020-00805-wopenalex-snapshot
An energy-efficient power management for heterogeneous servers in data centers
inferred← citeshttps://doi.org/10.1007/s00778-021-00663-8openalex-snapshot
Micro-architectural analysis of in-memory OLTP: Revisited
inferred← citeshttps://doi.org/10.1007/s10766-020-00687-7openalex-snapshot
DySHARQ: Dynamic Software-Defined Hardware-Managed Queues for Tile-Based Architectures
inferred← citeshttps://doi.org/10.1007/s11227-015-1439-3openalex-snapshot
Per-packet global congestion estimation for fast packet delivery in networks-on-chip
inferred← citeshttps://doi.org/10.1007/s11227-017-2024-8openalex-snapshot
Exploring grouped coherence for clustered hierarchical cache
inferred← citeshttps://doi.org/10.1007/s11227-019-02819-4openalex-snapshot
Design trade-offs for emerging HPC processors based on mobile market technology
inferred← citeshttps://doi.org/10.1016/bs.adcom.2015.10.002openalex-snapshot
Energy-Efficient Big Data Analytics in Datacenters
inferred← citeshttps://doi.org/10.1016/bs.adcom.2018.03.016openalex-snapshot
Dynamic Power Management for Dark Silicon Multicore Processors ☆ ☆Parts of this chapter describe the author's prior work in publications [1–3]. Consequently, some of the text and the figures in this chapter are adapted from these prior publications.
inferred← citeshttps://doi.org/10.1016/j.jpdc.2018.11.005openalex-snapshot
ReD: A reuse detector for content selection in exclusive shared last-level caches
inferred← citeshttps://doi.org/10.1038/s44287-024-00052-7openalex-snapshot
Neural architecture search for in-memory computing-based deep learning accelerators
inferred← citeshttps://doi.org/10.1093/comjnl/bxt129openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/cads.2017.8310674openalex-snapshot
NOC characteristics of cloud applications
inferred← citeshttps://doi.org/10.1109/hpca.2013.6522310openalex-snapshot
Navigating heterogeneous processors with market mechanisms
inferred← citeshttps://doi.org/10.1109/hpca.2014.6835943openalex-snapshot
Transportation-network-inspired network-on-chip
inferred← citeshttps://doi.org/10.1109/hpca.2014.6835975openalex-snapshot
Undersubscribed threading on clustered cache architectures
inferred← citeshttps://doi.org/10.1109/hpca.2015.7056037openalex-snapshot
Octopus-Man: QoS-driven task management for heterogeneous multicores in warehouse-scale computers
inferred← citeshttps://doi.org/10.1109/hpca.2015.7056045openalex-snapshot
High performing cache hierarchies for server workloads: Relaxing inclusion to capture the latency benefits of exclusive caches
inferred← citeshttps://doi.org/10.1109/hpca.2016.7446096openalex-snapshot
ChargeCache: Reducing DRAM latency by exploiting row access locality
inferred← citeshttps://doi.org/10.1109/hpca.2018.00021openalex-snapshot
Domino Temporal Data Prefetcher
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Amdahl's Law in Big Data Analytics: Alive and Kicking in TPCx-BB (BigBench)
inferred← citeshttps://doi.org/10.1109/hpca.2018.00061openalex-snapshot
Memory Hierarchy for Web Search
inferred← citeshttps://doi.org/10.1109/hpca.2018.00062openalex-snapshot
Characterizing Resource Sensitivity of Database Workloads
inferred← citeshttps://doi.org/10.1109/hpca.2019.00037openalex-snapshot
Enhancing Server Efficiency in the Face of Killer Microseconds
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Bingo Spatial Data Prefetcher
inferred← citeshttps://doi.org/10.1109/hpca61900.2025.00088openalex-snapshot
EFFACT: A Highly Efficient Full-Stack FHE Acceleration Platform
inferred← citeshttps://doi.org/10.1109/icac.2019.00031openalex-snapshot
Express-Lane Scheduling and Multithreading to Minimize the Tail Latency of Microservices
inferred← citeshttps://doi.org/10.1109/iccd.2012.6378637openalex-snapshot
Thermal characterization of cloud workloads on a power-efficient server-on-chip
inferred← citeshttps://doi.org/10.1109/iccd.2016.7753257openalex-snapshot
Accelerating pointer chasing in 3D-stacked memory: Challenges, mechanisms, evaluation
inferred← citeshttps://doi.org/10.1109/iccd56317.2022.00016openalex-snapshot
HyFarM: Task Orchestration on Hybrid Far Memory for High Performance Per Bit
inferred← citeshttps://doi.org/10.1109/iccd65941.2025.00102openalex-snapshot
FlexIO: A Scalable IO Chiplet Architecture with Flexible Memory Controller Mapping
inferred← citeshttps://doi.org/10.1109/icde.2014.6816692openalex-snapshot
ATraPos: Adaptive transaction processing on hardware Islands
inferred← citeshttps://doi.org/10.1109/icnc.2012.66openalex-snapshot
STRAIGHT: Realizing a Lightweight Large Instruction Window by Using Eventually Consistent Distributed Registers
inferred← citeshttps://doi.org/10.1109/igcc.2015.7393731openalex-snapshot
Rethinking manycore caches for scale-out applications
inferred← citeshttps://doi.org/10.1109/iiswc.2015.31openalex-snapshot
Evaluating the Combined Impact of Node Architecture and Cloud Workload Characteristics on Network Traffic and Performance/Cost
inferred← citeshttps://doi.org/10.1109/ipdps49936.2021.00065openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/isca45697.2020.00017openalex-snapshot
Divide and Conquer Frontend Bottleneck
inferred← citeshttps://doi.org/10.1109/isca59077.2024.00074openalex-snapshot
Compiler-Directed Whole-System Persistence
inferred← citeshttps://doi.org/10.1109/ispass.2013.6557146openalex-snapshot
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McSimA+: A manycore simulator with application-level+ simulation and detailed microarchitecture modeling
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Characterization and analysis of a web search benchmark
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A Characterization of the Effects of Software Instruction Prefetching on an Aggressive Front-end
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inferred← citeshttps://doi.org/10.1109/nocs.2013.6558410openalex-snapshot
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Market mechanisms for managing datacenters with heterogeneous microarchitectures
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Coherence domain restriction on large scale systems
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Invited - Heterogeneous datacenters
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inferred← citeshttps://doi.org/10.14257/astl.2016.121.73openalex-snapshot
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inferred← citeshttps://doi.org/10.31390/gradschool_dissertations.3918openalex-snapshot
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inferred← citeshttps://doi.org/10.3850/9783981537079_0980openalex-snapshot
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inferred← citeshttps://doi.org/10.48550/arxiv.1307.0320openalex-snapshot
BigDataBench: a Big Data Benchmark Suite from Web Search Engines
inferred← citeshttps://doi.org/10.48550/arxiv.1504.04974openalex-snapshot
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inferred← citeshttps://doi.org/10.48550/arxiv.2009.00715openalex-snapshot
A Survey on Recent Hardware Data Prefetching Approaches with An Emphasis on Servers
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Multi-Gigabyte On-Chip DRAM Caches for Servers
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High Performance Transaction Processing on Non-Uniform Hardware Topologies
inferred← citeshttps://doi.org/10.5821/dissertation-2117-96333openalex-snapshot
Improving the performance and energy-efficiency of virtual memory
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