On the public citation graph
Exploiting workload dynamics to improve SSD read latency via differentiated error correction codes
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1002/9780470181355openalex-snapshot
Nonvolatile Memory Technologies with Emphasis on Flash
inferredcites →https://doi.org/10.1017/cbo9780511800467openalex-snapshot
Algebraic Codes for Data Transmission
inferredcites →https://doi.org/10.1109/.2006.1629477openalex-snapshot
A High Performance Controller for NAND Flash-based Solid State Disk (NSSD)
inferredcites →https://doi.org/10.1109/4.499738openalex-snapshot
A double-level-V/sub th/ select gate array architecture for multilevel NAND flash memories
inferredcites →https://doi.org/10.1109/hpca.2010.5416650openalex-snapshot
A Hybrid solid-state storage architecture for the performance, energy consumption, and lifetime improvement
inferredcites →https://doi.org/10.1109/hpca.2011.5749736openalex-snapshot
I-CASH: Intelligently Coupled Array of SSD and HDD
inferredcites →https://doi.org/10.1109/hpcc.2009.69openalex-snapshot
Performance Analysis of NAND Flash-Based SSD for Designing a Hybrid Filesystem
inferredcites →https://doi.org/10.1109/iiswc.2008.4636097openalex-snapshot
Characterization of storage workload traces from production Windows Servers
inferredcites →https://doi.org/10.1109/irps.2009.5173269openalex-snapshot
Three bits per cell floating gate NAND flash memory technology for 30nm and beyond
inferredcites →https://doi.org/10.1109/isscc.2009.4977400openalex-snapshot
A 5.6MB/s 64Gb 4b/Cell NAND Flash memory in 43nm CMOS
inferredcites →https://doi.org/10.1109/jproc.2003.811702openalex-snapshot
Introduction to flash memory
inferredcites →https://doi.org/10.1109/jproc.2003.811709openalex-snapshot
On-chip error correcting techniques for new-generation flash memories
inferredcites →https://doi.org/10.1109/jproc.2003.818323openalex-snapshot
Nanotechnology enables a new memory growth model
inferredcites →https://doi.org/10.1109/jssc.2008.2007154openalex-snapshot
A 16 Gb 3-Bit Per Cell (X3) NAND Flash Memory on 56 nm Technology With 8 MB/s Write Rate
inferredcites →https://doi.org/10.1109/jssc.2008.917558openalex-snapshot
A Zeroing Cell-to-Cell Interference Page Architecture With Temporary LSB Storing and Parallel MSB Program Scheme for MLC NAND Flash Memories
inferredcites →https://doi.org/10.1109/jssc.2009.2014027openalex-snapshot
Novel Co-Design of NAND Flash Memory and NAND Flash Controller Circuits for Sub-30 nm Low-Power High-Speed Solid-State Drives (SSD)
inferredcites →https://doi.org/10.1109/mascots.2010.15openalex-snapshot
DiffECC: Improving SSD Read Performance Using Differentiated Error Correction Coding Schemes
inferredcites →https://doi.org/10.1109/tc.2008.224openalex-snapshot
Performance Trade-Offs in Using NVRAM Write Buffer for Flash Memory-Based Storage Devices
inferredcites →https://doi.org/10.1109/tce.2002.1010143openalex-snapshot
A space-efficient flash translation layer for CompactFlash systems
inferredcites →https://doi.org/10.1109/tce.2006.1649669openalex-snapshot
FAB: Flash-Aware Buffer Management Policy for Portable Media Players
inferredcites →https://doi.org/10.1109/tmag.2009.2024163openalex-snapshot
After Hard Drives—What Comes Next?
inferredcites →https://doi.org/10.1109/vlsic.2005.1469355openalex-snapshot
Non-volatile memory technologies for beyond 2010
inferredcites →https://doi.org/10.1145/1118299.1118382openalex-snapshot
Current trends in flash memory technology
inferredcites →https://doi.org/10.1145/1176887.1176911openalex-snapshot
A superblock-based flash translation layer for NAND flash memory
inferredcites →https://doi.org/10.1145/1233501.1233624openalex-snapshot
An adaptive two-level management for the flash translation layer in embedded systems
inferredcites →https://doi.org/10.1145/1278480.1278533openalex-snapshot
Endurance enhancement of flash-memory storage systems
inferredcites →https://doi.org/10.1145/1555754.1555790openalex-snapshot
The performance of PC solid-state disks (SSDs) as a function of bandwidth, concurrency, device architecture, and system organization
inferredcites →https://doi.org/10.1145/1559845.1559937openalex-snapshot
Advances in flash memory SSD technology for enterprise database applications
inferredcites →https://doi.org/10.1145/2093139.2093140openalex-snapshot
An adaptive write buffer management scheme for flash-based SSDs
inferredcites →https://doi.org/10.5555/1855511.1855519openalex-snapshot
Extending SSD lifetimes with disk-based write caches
inferredcites →https://doi.org/10.5555/1960475.1960481openalex-snapshot
CAFTL: a content-aware flash translation layer enhancing the lifespan of flash memory based solid state drives
inferredcites →https://doi.org/10.5555/1960475.1960482openalex-snapshot
Leveraging value locality in optimizing NAND flash-based SSDs
inferredcites →https://doi.org/10.5555/1960475.1960493openalex-snapshot
Exploiting memory device wear-out dynamics to improve NAND flash memory system performance
inferredcites →https://doi.org/10.5555/2208461.2208472openalex-snapshot
Optimizing NAND flash-based SSDs via retention relaxation
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1002/cpe.6044openalex-snapshot
Cost‐effectively improving solid state drive lifetime by hierarchical redundancy and heterogeneous memories
inferred← citeshttps://doi.org/10.1007/978-3-319-47099-3_2openalex-snapshot
Exploiting Cross-Layer Hotness Identification to Improve Flash Memory System Performance
inferred← citeshttps://doi.org/10.1016/j.sysarc.2025.103445openalex-snapshot
Set associative address mapping to improve data throughput and reduce tail latency in SSDs
inferred← citeshttps://doi.org/10.1109/jproc.2017.2735969openalex-snapshot
Reliability of nand-Based SSDs: What Field Studies Tell Us
inferred← citeshttps://doi.org/10.1109/nas.2015.7255200openalex-snapshot
Cost-effectively improving life endurance of MLC NAND flash SSDs via hierarchical data redundancy and heterogeneous flash memory
inferred← citeshttps://doi.org/10.1109/tc.2018.2839671openalex-snapshot
Access Characteristic Guided Read and Write Regulation on Flash Based Storage Systems
inferred← citeshttps://doi.org/10.1109/tcad.2014.2347929openalex-snapshot
A Reliability-Aware Address Mapping Strategy for NAND Flash Memory Storage Systems
inferred← citeshttps://doi.org/10.1109/tcad.2016.2626446openalex-snapshot
Asymmetric Error Rates of Cell States Exploration for Performance Improvement on Flash Memory Based Storage Systems
inferred← citeshttps://doi.org/10.1109/tcad.2023.3297971openalex-snapshot
Adaptive Differential Wearing for Read Performance Optimization on High-Density nand Flash Memory
inferred← citeshttps://doi.org/10.1109/tmscs.2016.2516015openalex-snapshot
A Real-Time Flash Translation Layer for NAND Flash Memory Storage Systems
inferred← citeshttps://doi.org/10.1109/tvlsi.2025.3551400openalex-snapshot
Revisiting Multiple ECC on High-Density NAND Flash memory
inferred← citeshttps://doi.org/10.1145/2699866openalex-snapshot
Enhancing the Reliability of MLC NAND Flash Memory Systems by Read Channel Optimization
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