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Design of efficient reversible logic-based binary and BCD adder circuits
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/978-1-4020-8919-0_9openalex-snapshot
Reversible Binary Coded Decimal Adders using Toffoli Gates
inferredcites →https://doi.org/10.1007/s10836-007-5042-2openalex-snapshot
Reversible Gates and Testability of One Dimensional Arrays of Molecular QCA
inferredcites →https://doi.org/10.1007/s10836-008-5078-yopenalex-snapshot
Detecting Multiple Faults in One-Dimensional Arrays of Reversible QCA Gates
inferredcites →https://doi.org/10.1007/s11128-009-0106-0openalex-snapshot
On figures of merit in reversible and quantum logic designs
inferredcites →https://doi.org/10.1016/j.mejo.2008.04.003openalex-snapshot
Efficient approaches for designing reversible Binary Coded Decimal adders
inferredcites →https://doi.org/10.1016/j.optlastec.2009.06.017openalex-snapshot
Mach–Zehnder interferometer-based all-optical reversible logic gate
inferredcites →https://doi.org/10.1016/j.sysarc.2005.05.005openalex-snapshot
Design of a compact reversible binary coded decimal adder circuit
inferredcites →https://doi.org/10.1016/j.sysarc.2007.01.007openalex-snapshot
Quantum ternary parallel adder/subtractor with partially-look-ahead carry
inferredcites →https://doi.org/10.1016/j.sysarc.2007.12.006openalex-snapshot
Optimized reversible binary-coded decimal adders
inferredcites →https://doi.org/10.1016/s0167-9260(02)00051-2openalex-snapshot
A reversible carry-look-ahead adder using control gates
inferredcites →https://doi.org/10.1093/comjnl/bxm042openalex-snapshot
Bi-Directional Synthesis of 4-Bit Reversible Circuits
inferredcites →https://doi.org/10.1093/comjnl/bxm116openalex-snapshot
An Introduction to Reversible Latches
inferredcites →https://doi.org/10.1103/physreva.32.3266openalex-snapshot
Reversible logic and quantum computers
inferredcites →https://doi.org/10.1103/physreva.53.2855openalex-snapshot
Five two-bit quantum gates are sufficient to implement the quantum Fredkin gate
inferredcites →https://doi.org/10.1103/physreva.54.147openalex-snapshot
Quantum networks for elementary arithmetic operations
inferredcites →https://doi.org/10.1109/acssc.2006.355056openalex-snapshot
Fault-Tolerant Reversible Circuits
inferredcites →https://doi.org/10.1109/ismvl.2005.9openalex-snapshot
Approaching the Physical Limits of Computing
inferredcites →https://doi.org/10.1109/ismvl.2008.42openalex-snapshot
Exact Synthesis of Elementary Quantum Gate Circuits for Reversible Functions with Don't Cares
inferredcites →https://doi.org/10.1109/isvlsi.2009.49openalex-snapshot
Design of Efficient Reversible Binary Subtractors Based on a New Reversible Gate
inferredcites →https://doi.org/10.1109/jproc.2009.2035451openalex-snapshot
Practical Strategies for Power-Efficient Computing Technologies
inferredcites →https://doi.org/10.1109/tcad.2003.811448openalex-snapshot
Synthesis of reversible logic circuits
inferredcites →https://doi.org/10.1109/tcad.2004.836735openalex-snapshot
Reversible Cascades With Minimal Garbage
inferredcites →https://doi.org/10.1109/tcad.2005.858352openalex-snapshot
Optimal synthesis of multiple output Boolean functions using a set of quantum gates by symbolic reachability analysis
inferredcites →https://doi.org/10.1109/tcad.2006.871622openalex-snapshot
An Algorithm for Synthesis of Reversible Logic Circuits
inferredcites →https://doi.org/10.1109/tcad.2009.2017215openalex-snapshot
Exact Multiple-Control Toffoli Network Synthesis With SAT Techniques
inferredcites →https://doi.org/10.1109/tnano.2009.2025038openalex-snapshot
Reversible Logic-Based Concurrently Testable Latches for Molecular QCA
inferredcites →https://doi.org/10.1142/s0219749909005523openalex-snapshot
MINIMIZATION AND OPTIMIZATION OF REVERSIBLE BCD-FULL ADDER/SUBTRACTOR USING GENETIC ALGORITHM AND DON'T CARE CONCEPT
inferredcites →https://doi.org/10.1145/1216396.1216399openalex-snapshot
Data structures and algorithms for simplifying reversible circuits
inferredcites →https://doi.org/10.1145/1324177.1324179openalex-snapshot
Arithmetic on a distributed-memory quantum multicomputer
inferredcites →https://doi.org/10.1145/1324177.1324181openalex-snapshot
Synthesis of reversible sequential elements
inferredcites →https://doi.org/10.1145/1837274.1837439openalex-snapshot
Reducing the number of lines in reversible circuits
inferredcites →https://doi.org/10.1145/1877745.1877748openalex-snapshot
Design of reversible sequential circuits optimizing quantum cost, delay, and garbage outputs
inferredcites →https://doi.org/10.1147/jrd.2010.2040930openalex-snapshot
A survey of hardware designs for decimal arithmetic
inferredcites →https://doi.org/10.26421/qic5.6-2openalex-snapshot
A linear-size quantum circuit for addition with no ancillary qubits
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Incoming claims: where this work appears in other papers’ reference lists and arguments.
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