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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/978-3-540-45234-8_7openalex-snapshot
ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix
inferredcites →https://doi.org/10.1007/s11265-008-0255-xopenalex-snapshot
Design of 100 μW Wireless Sensor Nodes for Biomedical Monitoring
inferredcites →https://doi.org/10.1109/asscc.2011.6123572openalex-snapshot
A micropower biomedical signal processor for mobile healthcare applications
inferredcites →https://doi.org/10.1109/biocas.2009.5372036openalex-snapshot
Low-power robust beat detection in ambulatory cardiac monitoring
inferredcites →https://doi.org/10.1109/fpl.2005.1515707openalex-snapshot
Custom implementation of the coarse-grained reconfigurable ADRES architecture for multimedia purposes
inferredcites →https://doi.org/10.1109/fpt.2012.6412156openalex-snapshot
SCC based modulo scheduling for coarse-grained reconfigurable processors
inferredcites →https://doi.org/10.1109/icip.2011.6116529openalex-snapshot
H.264/AVC UHD decoder implementation on multi-cluster platform using hybrid parallelization method
inferredcites →https://doi.org/10.1109/isscc.1994openalex-snapshot
Proceedings of IEEE International Solid-State Circuits Conference - ISSCC '94
inferredcites →https://doi.org/10.1109/isscc.2008.4523108openalex-snapshot
A 200μW Eight-Channel Acquisition ASIC for Ambulatory EEG Systems
inferredcites →https://doi.org/10.1109/isscc.2010.5433921openalex-snapshot
Millimeter-scale nearly perpetual sensor system with stacked battery and solar cells
inferredcites →https://doi.org/10.1109/isscc.2010.5434026openalex-snapshot
A 30µW Analog Signal Processor ASIC for biomedical signal monitoring
inferredcites →https://doi.org/10.1109/isscc.2011.5746341openalex-snapshot
A voltage-scalable biomedical signal processor running ECG using 13pJ/cycle at 1MHz and 0.4V
inferredcites →https://doi.org/10.1109/jssc.2009.2014707openalex-snapshot
A 1-V 450-nW Fully Integrated Programmable Biomedical Sensor Interface Chip
inferredcites →https://doi.org/10.1109/jssc.2011.2108910openalex-snapshot
Microwatt Embedded Processor Platform for Medical System-on-Chip Applications
inferredcites →https://doi.org/10.1145/1542452.1542456openalex-snapshot
Recurrence cycle aware modulo scheduling for coarse-grained reconfigurable architectures
inferredcites →https://doi.org/10.1145/2003695.2003711openalex-snapshot
A 36μW heartbeat-detection processor for a wireless sensor node
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-1-4419-6345-1_17openalex-snapshot
Coarse-Grained Reconfigurable Array Architectures
inferred← citeshttps://doi.org/10.1007/978-3-030-38991-8_3openalex-snapshot
Flexible Data Flow Architecture for Embedded Hardware Accelerators
inferred← citeshttps://doi.org/10.1007/s11554-017-0729-9openalex-snapshot
Software pipelining with CGA and proposed intrinsics on a reconfigurable processor for HEVC decoders
inferred← citeshttps://doi.org/10.1016/j.comcom.2021.01.026openalex-snapshot
Hybrid fog/cloud computing resource allocation: Joint consideration of limited communication resources and user credibility
inferred← citeshttps://doi.org/10.1016/j.micpro.2018.06.010openalex-snapshot
Energy efficient configuration unification and compression for CGRAs
inferred← citeshttps://doi.org/10.1016/j.sysarc.2019.05.007openalex-snapshot
Random test program generation for verification and validation of the Samsung Reconfigurable Processor
inferred← citeshttps://doi.org/10.1016/j.sysarc.2024.103243openalex-snapshot
Coarse-grained reconfigurable architectures for radio baseband processing: A survey
inferred← citeshttps://doi.org/10.1016/j.vlsi.2018.07.005openalex-snapshot
An efficient hardware architecture for detection of vowel-like regions in speech signal
inferred← citeshttps://doi.org/10.1016/j.vlsi.2018.11.001openalex-snapshot
Architectures and algorithms for on-device user customization of CNNs
inferred← citeshttps://doi.org/10.1038/s42254-022-00440-8openalex-snapshot
Ising machines as hardware solvers of combinatorial optimization problems
inferred← citeshttps://doi.org/10.1109/access.2020.3012084openalex-snapshot
A Survey on Coarse-Grained Reconfigurable Architectures From a Performance Perspective
inferred← citeshttps://doi.org/10.1109/asap.2017.7995277openalex-snapshot
CGRA-ME: A unified framework for CGRA modelling and exploration
inferred← citeshttps://doi.org/10.1109/asap52443.2021.00043openalex-snapshot
Double-Pumping the Interconnect for Area Reduction in Coarse-Grained Reconfigurable Arrays
inferred← citeshttps://doi.org/10.1109/dac.2018.8465799openalex-snapshot
An Architecture-Agnostic Integer Linear Programming Approach to CGRA Mapping
inferred← citeshttps://doi.org/10.1109/dac18074.2021.9586267openalex-snapshot
Formulating Data-arrival Synchronizers in Integer Linear Programming for CGRA Mapping
inferred← citeshttps://doi.org/10.1109/dsd.2018.00087openalex-snapshot
Design and Evaluation of a Low Power CGRA Accelerator for Biomedical Signal Processing
inferred← citeshttps://doi.org/10.1109/dsd53832.2021.00015openalex-snapshot
An Open-Source Framework for the Generation of RISC-V Processor + CGRA Accelerator Systems
inferred← citeshttps://doi.org/10.1109/dsd64264.2024.00061openalex-snapshot
DA-CGRA: Domain-Aware Heterogeneous Coarse-Grained Reconfigurable Architecture for the Edge
inferred← citeshttps://doi.org/10.1109/fpl.2013.6645594openalex-snapshot
A hardware complete detection mechanism for an energy efficient reconfigurable accelerator CMA
inferred← citeshttps://doi.org/10.1109/fpt.2013.6718383openalex-snapshot
A speculative gather system for Cool Mega-Array
inferred← citeshttps://doi.org/10.1109/fpt.2018.00028openalex-snapshot
Compact Area and Performance Modelling for CGRA Architecture Evaluation
inferred← citeshttps://doi.org/10.1109/hpca.2015.7056040openalex-snapshot
NDA: Near-DRAM acceleration architecture leveraging commodity DRAM devices and standard memory modules
inferred← citeshttps://doi.org/10.1109/icassp.2016.7471836openalex-snapshot
Efficient deblocking filter implementation on reconfigurable processor
inferred← citeshttps://doi.org/10.1109/iccad45719.2019.8942148openalex-snapshot
4D-CGRA: Introducing Branch Dimension to Spatio-Temporal Application Mapping on CGRAs
inferred← citeshttps://doi.org/10.1109/iccad57390.2023.10323612openalex-snapshot
FLEX: Introducing FLEXible Execution on CGRA with Spatio-Temporal Vector Dataflow
inferred← citeshttps://doi.org/10.1109/icfpt47387.2019.00018openalex-snapshot
A Coarse-Grained Reconfigurable Architecture with a Fault Tolerant Non-Volatile Configurable Memory
inferred← citeshttps://doi.org/10.1109/icfpt56656.2022.9974339openalex-snapshot
Energy Efficient Design of Coarse-Grained Reconfigurable Architectures: Insights, Trends and Challenges
inferred← citeshttps://doi.org/10.1109/ipdpsw55747.2022.00113openalex-snapshot
Exploration Framework for Synthesizable CGRAs Targeting HPC: Initial Design and Evaluation
inferred← citeshttps://doi.org/10.1109/isca52012.2021.00084openalex-snapshot
Snafu: An Ultra-Low-Power, Energy-Minimal CGRA-Generation Framework and Architecture
inferred← citeshttps://doi.org/10.1109/iscas.2016.7527340openalex-snapshot
Intra mode power saving methodology for CGRA-based reconfigurable processor architectures
inferred← citeshttps://doi.org/10.1109/iscas51556.2021.9401461openalex-snapshot
BioCare: An Energy-Efficient CGRA for Bio-Signal Processing at the Edge
inferred← citeshttps://doi.org/10.1109/isqed60706.2024.10528709openalex-snapshot
Dual Use Circuitry for Early Failure Warning and Test
inferred← citeshttps://doi.org/10.1109/jproc.2014.2386883openalex-snapshot
Reconfigurable Computing Architectures
inferred← citeshttps://doi.org/10.1109/reconfig.2017.8279789openalex-snapshot
Evaluation of CGRA architecture for real-time processing of biological signals on wearable devices
inferred← citeshttps://doi.org/10.1109/tbcas.2015.2480035openalex-snapshot
A 0.04 mm Buck-Boost DC-DC Converter for Biomedical Implants Using Adaptive Gain and Discrete Frequency Scaling Control
inferred← citeshttps://doi.org/10.1109/tbcas.2021.3120965openalex-snapshot
Multi-Level Optimization of an Ultra-Low Power BrainWave System for Non-Convulsive Seizure Detection
inferred← citeshttps://doi.org/10.1109/tc.2023.3257504openalex-snapshot
Acceleration of Control Intensive Applications on Coarse-Grained Reconfigurable Arrays for Embedded Systems
inferred← citeshttps://doi.org/10.1109/tcad.2018.2834397openalex-snapshot
An Energy-Efficient Integrated Programmable Array Accelerator and Compilation Flow for Near-Sensor Ultralow Power Processing
inferred← citeshttps://doi.org/10.1109/tcad.2018.2857278openalex-snapshot
Auto-Tuning CNNs for Coarse-Grained Reconfigurable Array-Based Accelerators
inferred← citeshttps://doi.org/10.1109/tcad.2021.3132551openalex-snapshot
HiMap: Fast and Scalable High-Quality Mapping on CGRA via Hierarchical Abstraction
inferred← citeshttps://doi.org/10.1109/tcad.2024.3383349openalex-snapshot
GREEN: An Approximate SIMD/MIMD CGRA for Energy-Efficient Processing at the Edge
inferred← citeshttps://doi.org/10.1109/tcad.2024.3520024openalex-snapshot
SubMap: A Partial Mapping Strategy for CGRA Based on sub-CGRA Exploration
inferred← citeshttps://doi.org/10.1109/tpds.2020.3007492openalex-snapshot
Pattern-Based Dynamic Compilation System for CGRAs With Online Configuration Transformation
inferred← citeshttps://doi.org/10.1109/tvlsi.2016.2585603openalex-snapshot
Efficient Partial Online Synthesis of Special Instructions for Reconfigurable Processors
inferred← citeshttps://doi.org/10.1109/tvlsi.2017.2754272openalex-snapshot
An Energy-Efficient Programmable Manycore Accelerator for Personalized Biomedical Applications
inferred← citeshttps://doi.org/10.1145/2902961.2902986openalex-snapshot
Low-Power Manycore Accelerator for Personalized Biomedical Applications
inferred← citeshttps://doi.org/10.1145/2996468openalex-snapshot
The First 25 Years of the FPL Conference
inferred← citeshttps://doi.org/10.1145/3136825.3136885openalex-snapshot
Element-key table based complex key generation (E-CKG) for IoT based health care networks
inferred← citeshttps://doi.org/10.1145/3162018openalex-snapshot
Improving Energy Efficiency of Coarse-Grain Reconfigurable Arrays Through Modulo Schedule Compression/Decompression
inferred← citeshttps://doi.org/10.1145/3211332.3211342openalex-snapshot
Verification of coarse-grained reconfigurable arrays through random test programs
inferred← citeshttps://doi.org/10.1145/3316781.3317745openalex-snapshot
A General Pattern-Based Dynamic Compilation Framework for Coarse-Grained Reconfigurable Architectures
inferred← citeshttps://doi.org/10.1145/3394885.3431601openalex-snapshot
Area Efficient Functional Locking through Coarse Grained Runtime Reconfigurable Architectures
inferred← citeshttps://doi.org/10.1145/3558394openalex-snapshot
Improving Energy Efficiency of CGRAs with Low-Overhead Fine-Grained Power Domains
inferred← citeshttps://doi.org/10.1145/3656642openalex-snapshot
R-Blocks: an Energy-Efficient, Flexible, and Programmable CGRA
inferred← citeshttps://doi.org/10.1145/3663675openalex-snapshot
SAT-Based Exact Modulo Scheduling Mapping for Resource-Constrained CGRAs
inferred← citeshttps://doi.org/10.1145/3669940.3707230openalex-snapshot
Enhancing CGRA Efficiency Through Aligned Compute and Communication Provisioning
inferred← citeshttps://doi.org/10.1145/3677118openalex-snapshot
An Overview of FPGA-inspired Obfuscation Techniques
inferred← citeshttps://doi.org/10.1145/3721294openalex-snapshot
CTScan: A CGRA-based Platform for the Emulation of Power Side-Channel Attacks on Edge CPUs
inferred← citeshttps://doi.org/10.1145/3765623openalex-snapshot
Adaptive Computing in Memory Meets Conventional Batteryless Platforms
inferred← citeshttps://doi.org/10.1145/3829368openalex-snapshot
A Perspective on the Topics from a Selection of Papers from the First 20 Years of the International Symposium on Applied Reconfigurable Computing (ARC)
inferred← citeshttps://doi.org/10.1201/9781351229067-7openalex-snapshot
Context-Aware Biomedical Smart Systems
inferred← citeshttps://doi.org/10.17762/turcomat.v12i4.1225openalex-snapshot
CGRA MODULO SCHEDULING FOR ACHIEVING BETTER PERFORMANCE AND INCREASED EFFICIENCY
inferred← citeshttps://doi.org/10.23919/date.2018.8342173openalex-snapshot
Optimizing the data placement and transformation for multi-bank CGRA computing system
inferred← citeshttps://doi.org/10.23919/date51398.2021.9473916openalex-snapshot
HiMap: Fast and Scalable High-Quality Mapping on CGRA via Hierarchical Abstraction
inferred← citeshttps://doi.org/10.5555/3049832.3049854openalex-snapshot
A space- and energy-efficient code Compression/Decompression technique for coarse-grained reconfigurable architectures
inferred← citeshttps://doi.org/10.70675/7775c970za680z4d00zacfbz035b8407c34copenalex-snapshot
Architecture and Programming Model Support for Reconfigurable Accelerators in Multi-Core Embedded Systems
inferred← citeshttps://doi.org/10.7251/els1418003lopenalex-snapshot
Energy Efficient Multi-Core Processing
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