On the public citation graph

Scaling Input Stimulus Generation through Hybrid Static and Dynamic Analysis of RTL

https://doi.org/10.1145/2676549
0 signed · 66 inferred · view as graph

Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.

Is this your work? Sign in with ORCID and put your name on the claims that are yours.
Claim with ORCID
Reference health. See whether every reference in this work resolves to a known work and none has been retracted — and get a dated CiteStamped badge you can embed.
See reference health

What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/978-1-4615-3190-6_3openalex-snapshot
Symbolic Model Checking
inferredcites →https://doi.org/10.1007/978-3-540-24605-3_7openalex-snapshot
SAT Based Predicate Abstraction for Hardware Verification
inferredcites →https://doi.org/10.1007/978-3-540-69149-5_27openalex-snapshot
Model Checking: Back and Forth between Hardware and Software
inferredcites →https://doi.org/10.1007/978-3-540-77966-7_3openalex-snapshot
From Hardware Verification to Software Verification: Re-use and Re-learn
inferredcites →https://doi.org/10.1007/978-3-540-78800-3_27openalex-snapshot
RWset: Attacking Path Explosion in Constraint-Based Test Generation
inferredcites →https://doi.org/10.1007/978-3-642-02658-4_41openalex-snapshot
Reducing Test Inputs Using Information Partitions
inferredcites →https://doi.org/10.1007/978-3-642-31424-7_23openalex-snapshot
Software Model Checking via IC3
inferredcites →https://doi.org/10.1023/a:1011189608077openalex-snapshot
SIVA: A System for Coverage-Directed State Space Search
inferredcites →https://doi.org/10.1023/a:1022885523034openalex-snapshot
A Hierarchical Test Generation Approach Using Program Slicing Techniques on Hardware Description Languages
inferredcites →https://doi.org/10.1109/43.913758openalex-snapshot
Automatic test pattern generation for functional register-transfer level circuits using assignment decision diagrams
inferredcites →https://doi.org/10.1109/ase.2008.69openalex-snapshot
Heuristics for Scalable Dynamic Test Generation
inferredcites →https://doi.org/10.1109/date.2005.162openalex-snapshot
Functional Coverage Driven Test Generation for Validation of Pipelined Processors
inferredcites →https://doi.org/10.1109/date.2006.244050openalex-snapshot
Distance-Guided Hybrid Verification with GUIDO
inferredcites →https://doi.org/10.1109/date.2011.5763253openalex-snapshot
Efficient validation input generation in RTL by hybridized source code analysis
inferredcites →https://doi.org/10.1109/date.2012.6176423openalex-snapshot
Automated generation of directed tests for transition coverage in cache coherence protocols
inferredcites →https://doi.org/10.1109/hldvt.2007.4392805openalex-snapshot
Coverage-directed test generation through automatic constraint extraction
inferredcites →https://doi.org/10.1109/hldvt.2009.5340179openalex-snapshot
STAR: Generating input vectors for design validation by static analysis of RTL
inferredcites →https://doi.org/10.1109/iccd.2001.955007openalex-snapshot
A functional validation technique: biased-random simulation guided by observability-based coverage
inferredcites →https://doi.org/10.1109/memcod.2011.5970527openalex-snapshot
EFSM-based model-driven approach to concolic testing of system-level design
inferredcites →https://doi.org/10.1109/mtv.2007.13openalex-snapshot
A Scalable Symbolic Simulator for Verilog RTL
inferredcites →https://doi.org/10.1109/tc.1986.1676819openalex-snapshot
Graph-Based Algorithms for Boolean Function Manipulation
inferredcites →https://doi.org/10.1109/tse.1976.233817openalex-snapshot
A System to Generate Test Data and Symbolically Execute Programs
inferredcites →https://doi.org/10.1145/1064978.1065036openalex-snapshot
DART
inferredcites →https://doi.org/10.1145/1065010.1065036openalex-snapshot
DART
inferredcites →https://doi.org/10.1145/1065579.1065697openalex-snapshot
Word level predicate abstraction and refinement for verifying RTL verilog
inferredcites →https://doi.org/10.1145/1081706.1081750openalex-snapshot
CUTE
inferredcites →https://doi.org/10.1145/1119772.1119790openalex-snapshot
SAT-based sequential depth computation
inferredcites →https://doi.org/10.1145/1120725.1120858openalex-snapshot
An efficient control-oriented coverage metric
inferredcites →https://doi.org/10.1145/1127908.1127991openalex-snapshot
Test generation using SAT-based bounded model checking for validation of pipelined processors
inferredcites →https://doi.org/10.1145/1180405.1180445openalex-snapshot
EXE
inferredcites →https://doi.org/10.1145/1190215.1190226openalex-snapshot
Compositional dynamic test generation
inferredcites →https://doi.org/10.1145/1190216.1190226openalex-snapshot
Compositional dynamic test generation
inferredcites →https://doi.org/10.1145/1233501.1233662openalex-snapshot
Decomposing image computation for symbolic reachability analysis using control flow information
inferredcites →https://doi.org/10.1145/1278480.1278498openalex-snapshot
An effective guidance strategy for abstraction-guided simulation
inferredcites →https://doi.org/10.1145/1366110.1366145openalex-snapshot
Coverage-driven automatic test generation for uml activity diagrams
inferredcites →https://doi.org/10.1145/1367045.1367051openalex-snapshot
Specification-driven directed test generation for validation of pipelined processors
inferredcites →https://doi.org/10.1145/1391469.1391507openalex-snapshot
Tunneling and slicing
inferredcites →https://doi.org/10.1145/1403375.1403473openalex-snapshot
Efficient design validation based on cultural algorithms
inferredcites →https://doi.org/10.1145/1706299.1706307openalex-snapshot
Compositional may-must program analysis
inferredcites →https://doi.org/10.1145/2254064.2254088openalex-snapshot
Efficient state merging in symbolic execution
inferredcites →https://doi.org/10.1145/309847.310023openalex-snapshot
Simulation vector generation from HDL descriptions for observability-enhanced statement coverage
inferredcites →https://doi.org/10.1145/378239.378278openalex-snapshot
Symbolic RTL simulation
inferredcites →https://doi.org/10.1145/775832.775907openalex-snapshot
Coverage directed test generation for functional verification using bayesian networks
inferredcites →https://doi.org/10.5555/1855741.1855756openalex-snapshot
KLEE: unassisted and automatic generation of high-coverage tests for complex systems programs
inferredcites →https://doi.org/10.5555/1870926.1871074openalex-snapshot
GoldMine: automatic assertion generation using data mining and static analysis

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/978-3-030-02807-7_1openalex-snapshot
Security and Trust Verification of IoT SoCs
inferred← citeshttps://doi.org/10.1007/978-3-662-49674-9_38openalex-snapshot
v2c – A Verilog to C Translator
inferred← citeshttps://doi.org/10.1016/j.vlsi.2022.05.001openalex-snapshot
Grammar-based fuzz testing for microprocessor RTL design
inferred← citeshttps://doi.org/10.1109/access.2019.2892649openalex-snapshot
A Specification-Based Semi-Formal Functional Verification Method by a Stage Transition Graph Model
inferred← citeshttps://doi.org/10.1109/icccn65249.2025.11133817openalex-snapshot
Enabling Symbolic Execution for Hardware TCP/IP Stack based on AMD Vitis HLS
inferred← citeshttps://doi.org/10.1109/iccd.2015.7357082openalex-snapshot
SI-SMART: Functional test generation for RTL circuits using loop abstraction and learning recurrence relationships
inferred← citeshttps://doi.org/10.1109/iccd.2017.36openalex-snapshot
QUEBS: Qualifying Event Based Search in Concolic Testing for Validation of RTL Models
inferred← citeshttps://doi.org/10.1109/icrc.2017.8123645openalex-snapshot
Still a Fight to Get It Right: Verification in the Era of Machine Learning
inferred← citeshttps://doi.org/10.1109/isqed65160.2025.11014344openalex-snapshot
Assertion-Based Trojan Localization Using Iterative Path Sensitization
inferred← citeshttps://doi.org/10.1109/isvlsi.2015.107openalex-snapshot
Hardware Verification Using Software Analyzers
inferred← citeshttps://doi.org/10.1109/tc.2020.2997644openalex-snapshot
Scalable Concolic Testing of RTL Models
inferred← citeshttps://doi.org/10.1109/test.2018.8624854openalex-snapshot
Scalable Hardware Trojan Activation by Interleaving Concrete Simulation and Symbolic Execution
inferred← citeshttps://doi.org/10.1145/3314221.3314601openalex-snapshot
A complete formal semantics of x86-64 user-level instruction set architecture
inferred← citeshttps://doi.org/10.1145/3638046openalex-snapshot
Directed Test Generation for Hardware Validation: A Survey
inferred← citeshttps://doi.org/10.1145/3655621openalex-snapshot
Incremental Concolic Testing of Register-Transfer Level Designs
inferred← citeshttps://doi.org/10.15514/ispras-2015-27(1)-6openalex-snapshot
A Survey of Methods for Model Extraction from HDL Descriptions
inferred← citeshttps://doi.org/10.23919/date.2018.8342260openalex-snapshot
Directed test generation using concolic testing on RTL models
inferred← citeshttps://doi.org/10.23919/date.2019.8714989openalex-snapshot
Automated Activation of Multiple Targets in RTL Models using Concolic Testing
inferred← citeshttps://doi.org/10.23919/date56975.2023.10136970openalex-snapshot
STSearch: State Tracing-based Search Heuristics for RTL Validation
inferred← citeshttps://doi.org/10.3850/9783981537079_0274openalex-snapshot
Unbounded Safety Verification for Hardware Using Software Analyzers
inferred← citeshttps://doi.org/10.48550/arxiv.1601.05850openalex-snapshot
Regression Testing of Virtual Prototypes Using Symbolic Execution
Editorial review for independent work. ICSAC — the Institute for Complexity Science and Advanced Computing — runs a structured editorial panel for researchers publishing outside journals, and publishes on CiteStamp rails. Submission is free and goes through ORCID: icsacinstitute.org/submit.