On the public citation graph
Measuring Microarchitectural Details of Multi- and Many-Core Memory Systems through Microbenchmarking
0 signed · 44 inferred · view as graph
Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.
Is this your work? Sign in with ORCID and put your name on the
claims that are yours.
Reference health. See whether every reference in this work resolves to a
known work and none has been retracted — and get a dated CiteStamped
badge you can embed.
What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/3-540-35767-x_25openalex-snapshot
The Specification of Source-to-Source Transformations for the Compile-Time Optimization of Parallel Object-Oriented Scientific Applications
inferredcites →https://doi.org/10.1007/978-3-540-93799-9_5openalex-snapshot
Investigating Cache Parameters of x86 Family Processors
inferredcites →https://doi.org/10.1016/j.sysarc.2008.02.004openalex-snapshot
Memory hierarchy performance measurement of commercial dual-core desktop processors
inferredcites →https://doi.org/10.1109/hpca.2007.346185openalex-snapshot
Feedback Directed Prefetching: Improving the Performance and Bandwidth-Efficiency of Hardware Prefetchers
inferredcites →https://doi.org/10.1109/ipdpsw.2013.231openalex-snapshot
Compiler-Based Data Prefetching and Streaming Non-temporal Store Generation for the Intel(R) Xeon Phi(TM) Coprocessor
inferredcites →https://doi.org/10.1109/ispass.2010.5452013openalex-snapshot
Demystifying GPU microarchitecture through microbenchmarking
inferredcites →https://doi.org/10.1109/ispass.2011.5762738openalex-snapshot
Mechanistic-empirical processor performance modeling for constructing CPI stacks on real hardware
inferredcites →https://doi.org/10.1109/micro.1996openalex-snapshot
Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture. MICRO 29
inferredcites →https://doi.org/10.1109/micro.2006.44openalex-snapshot
Scalable Cache Miss Handling for High Memory-Level Parallelism
inferredcites →https://doi.org/10.1109/pact.2009.22openalex-snapshot
Memory Performance and Cache Coherency Effects on an Intel Nehalem Multiprocessor System
inferredcites →https://doi.org/10.1109/qest.2004.33openalex-snapshot
Performance analysis with BenchIT: portable, flexible, easy to use
inferredcites →https://doi.org/10.1145/1022969.1022971openalex-snapshot
Interaction cost and shotgun profiling
inferredcites →https://doi.org/10.1145/1168857.1168880openalex-snapshot
A performance counter architecture for computing accurate CPI components
inferredcites →https://doi.org/10.1145/1188455openalex-snapshot
Proceedings of the 2006 ACM/IEEE conference on Supercomputing - SC '06
inferredcites →https://doi.org/10.1145/143365.143488openalex-snapshot
Design and evaluation of a compiler algorithm for prefetching
inferredcites →https://doi.org/10.1145/1504176.1504208openalex-snapshot
A compiler-directed data prefetching scheme for chip multiprocessors
inferredcites →https://doi.org/10.1145/1669112.1669154openalex-snapshot
Coordinated control of multiple prefetchers in multi-core systems
inferredcites →https://doi.org/10.1145/1950365.1950411openalex-snapshot
Inter-core prefetching for multicore processors using migrating helper threads
inferredcites →https://doi.org/10.1145/2000064.2000107openalex-snapshot
Rapid identification of architectural bottlenecks via precise event counting
inferredcites →https://doi.org/10.1145/2133382.2133384openalex-snapshot
When Prefetching Works, When It Doesn’t, and Why
inferredcites →https://doi.org/10.1145/2597652.2597660openalex-snapshot
Multi-stage coordinated prefetching for present-day processors
inferredcites →https://doi.org/10.5555/1413370.1413402openalex-snapshot
Benchmarking GPUs to tune dense linear algebra
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-3-319-57972-6_12openalex-snapshot
Evaluation of a Master-Slave Parallel Evolutionary Algorithm Applied to Artificial Intelligence for Games in the Xeon-Phi Many-Core Platform
inferred← citeshttps://doi.org/10.1007/978-3-319-58943-5_55openalex-snapshot
Dealing with Layers of Obfuscation in Pseudo-Uniform Memory Architectures
inferred← citeshttps://doi.org/10.1007/s11432-015-0989-3openalex-snapshot
Characterizing and optimizing Java-based HPC applications on Intel many-core architecture
inferred← citeshttps://doi.org/10.1016/j.sysarc.2023.102877openalex-snapshot
Exploiting the microarchitectural leakage of prefetching activities for side-channel attacks
inferred← citeshttps://doi.org/10.1109/access.2017.2689077openalex-snapshot
Terahertz Band Intra-Chip Communications: Can Wireless Links Scale Modern x86 CPUs?
inferred← citeshttps://doi.org/10.1109/icppw.2015.25openalex-snapshot
Open JDK Meets Xeon Phi: A Comprehensive Study of Java HPC on Intel Many-Core Architecture
inferred← citeshttps://doi.org/10.1109/ispass55109.2022.00002openalex-snapshot
Performance Analysis and Optimization with Little’s Law
inferred← citeshttps://doi.org/10.1109/nas.2019.8834726openalex-snapshot
HCMA: Supporting High Concurrency of Memory Accesses with Scratchpad Memory in FPGAs
inferred← citeshttps://doi.org/10.1109/rtas48715.2020.000-6openalex-snapshot
Slow and Steady: Measuring and Tuning Multicore Interference
inferred← citeshttps://doi.org/10.1109/sies.2016.7509423openalex-snapshot
MIPP: A microbenchmark suite for performance, power, and energy consumption characterization of GPU architectures
inferred← citeshttps://doi.org/10.1109/uic-atc-scalcom-cbdcom-iop-smartworld.2016.0179openalex-snapshot
MyThOS — Scalable OS Design for Extremely Parallel Applications
inferred← citeshttps://doi.org/10.1145/2897937.2897972openalex-snapshot
A quantitative analysis on microarchitectures of modern CPU-FPGA platforms
inferred← citeshttps://doi.org/10.1145/3061639.3062304openalex-snapshot
Power-aware Performance Tuning of GPU Applications Through Microbenchmarking
inferred← citeshttps://doi.org/10.1145/3091966.3091975openalex-snapshot
Efficient array slicing on the Intel Xeon Phi coprocessor
inferred← citeshttps://doi.org/10.1145/3294054openalex-snapshot
In-Depth Analysis on Microarchitectures of Modern Heterogeneous CPU-FPGA Platforms
inferred← citeshttps://doi.org/10.1145/3431920.3439284openalex-snapshot
Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers through Microbenchmarking
inferred← citeshttps://doi.org/10.1145/3497776.3517783openalex-snapshot
Software pre-execution for irregular memory accesses in the HBM era
inferred← citeshttps://doi.org/10.1145/3517131openalex-snapshot
Demystifying the Soft and Hardened Memory Systems of Modern FPGAs for Software Programmers through Microbenchmarking
Editorial review for independent work. ICSAC — the Institute for Complexity
Science and Advanced Computing — runs a structured editorial panel for researchers
publishing outside journals, and publishes on CiteStamp rails. Submission is free
and goes through ORCID: icsacinstitute.org/submit.