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Scalable Cache Miss Handling for High Memory-Level Parallelism
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1109/conect.2004.1375194openalex-snapshot
Performance evaluation of the Cray X1 distributed shared memory architecture
inferredcites →https://doi.org/10.1109/hpca.2001.903254openalex-snapshot
JETTY: filtering snoops for reduced energy consumption in SMP servers
inferredcites →https://doi.org/10.1109/hpca.2003.1183532openalex-snapshot
Runahead execution: an alternative to very large instruction windows for out-of-order processors
inferredcites →https://doi.org/10.1109/hpca.2004.10008openalex-snapshot
Out-of-Order Commit Processors
inferredcites →https://doi.org/10.1109/hpca.2005.9openalex-snapshot
Checkpointed early load retirement
inferredcites →https://doi.org/10.1109/isca.1994.288148openalex-snapshot
Complexity/performance tradeoffs with non-blocking loads
inferredcites →https://doi.org/10.1109/isca.2005.46openalex-snapshot
Scalable Load and Store Processing in Latency Tolerant Processors
inferredcites →https://doi.org/10.1109/micro.2001.991129openalex-snapshot
Handling long-latency loads in a simultaneous multithreading processor
inferredcites →https://doi.org/10.1109/micro.2002.1176234openalex-snapshot
Cherry: Checkpointed early resource recycling in out-of-order microprocessors
inferredcites →https://doi.org/10.1109/micro.2003.1253244openalex-snapshot
Scalable hardware memory disambiguation for high ILP processors
inferredcites →https://doi.org/10.1109/micro.2003.1253245openalex-snapshot
Reducing design complexity of the load/store queue
inferredcites →https://doi.org/10.1109/micro.2003.1253246openalex-snapshot
Checkpoint processing and recovery: towards scalable large instruction window processors
inferredcites →https://doi.org/10.1109/mm.2004.87openalex-snapshot
Scalable hardware memory disambiguation for high-ILP processors
inferredcites →https://doi.org/10.1109/mm.2005.20openalex-snapshot
Performance Evaluation of the Cray X1 Distributed Shared-Memory Architecture
inferredcites →https://doi.org/10.1109/superc.1988.44672openalex-snapshot
The design of a lockup-free cache for high-performance multiprocessors
inferredcites →https://doi.org/10.1145/1028176.1006708openalex-snapshot
Microarchitecture Optimizations for Exploiting Memory-Level Parallelism
inferredcites →https://doi.org/10.1145/106972.106980openalex-snapshot
High-bandwidth data memory systems for superscalar processors
inferredcites →https://doi.org/10.1145/1080695.1070007openalex-snapshot
Scalable Load and Store Processing in Latency Tolerant Processors
inferredcites →https://doi.org/10.1145/191995.192029openalex-snapshot
Complexity/performance tradeoffs with non-blocking loads
inferredcites →https://doi.org/10.1145/263580.263595openalex-snapshot
Data caches for superscalar processors
inferredcites →https://doi.org/10.1145/285930.285979openalex-snapshot
Lockup-free instruction fetch/prefetch cache organization
inferredcites →https://doi.org/10.1145/782814.782859openalex-snapshot
Enhancing memory level parallelism via recovery-free value prediction
inferredcites →https://doi.org/10.5555/563998.564038openalex-snapshot
Handling long-latency loads in a simultaneous multithreading processor
inferredcites →https://doi.org/10.5555/62972.63017openalex-snapshot
The design of a lockup-free cache for high-performance multiprocessors
inferredcites →https://doi.org/10.5555/956417.956554openalex-snapshot
Checkpoint processing and recovery: towards scalable large instruction window processors
inferredcites →https://doi.org/10.5555/956417.956555openalex-snapshot
Reducing design complexity of the load/store queue
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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A High Performance Adaptive Miss Handling Architecture for Chip Multiprocessors
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A Study on Modeling and Optimization of Memory Systems
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System implications of LLC MSHRs in scalable memory systems
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Fair memory access scheduling algorithms for multicore processors
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inferred← citeshttps://doi.org/10.1109/asp-dac66049.2026.11420550openalex-snapshot
NBCache: An Efficient and Scalable Non-Blocking Cache for Coherent Multi-Chiplet Systems
inferred← citeshttps://doi.org/10.1109/ccgrid68966.2026.00055openalex-snapshot
S-MSHR: A Scalable MSHR Architecture Using Cache Tag Data-Ready Bits and Index Queues
inferred← citeshttps://doi.org/10.1109/dsd.2012.95openalex-snapshot
On-Package Scalability of RF and Inductive Memory Controllers
inferred← citeshttps://doi.org/10.1109/fccm51124.2021.00019openalex-snapshot
GORDON: Benchmarking Optane DC Persistent Memory Modules on FPGAs
inferred← citeshttps://doi.org/10.1109/host45689.2020.9300259openalex-snapshot
Hardware/Software Obfuscation against Timing Side-channel Attack on a GPU
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Handling branches in TLS systems with Multi-Path Execution
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inferred← citeshttps://doi.org/10.1109/hpca56546.2023.10071125openalex-snapshot
CARE: A Concurrency-Aware Enhanced Lightweight Cache Management Framework
inferred← citeshttps://doi.org/10.1109/hpcc.2012.26openalex-snapshot
High Performance Memory Requests Scheduling Technique for Multicore Processors
inferred← citeshttps://doi.org/10.1109/hpcc64274.2024.00037openalex-snapshot
Solution to MSHR contention in multi-core real-time systems based on software hardware collaboration
inferred← citeshttps://doi.org/10.1109/iccd.2012.6378638openalex-snapshot
RFiop: RF-memory path to address on-package I/O pad and memory controller scalability
inferred← citeshttps://doi.org/10.1109/iccd.2018.00046openalex-snapshot
CART: Cache Access Reordering Tree for Efficient Cache and Memory Accesses in GPUs
inferred← citeshttps://doi.org/10.1109/iccsn.2011.6013954openalex-snapshot
How many entries we need in miss handling architectures of L1 and L2 cache?
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Polynesia: Enabling High-Performance and Energy-Efficient Hybrid Transactional/Analytical Databases with Hardware/Software Co-Design
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3D-Stacked Memory Architectures for Multi-core Processors
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Accel-Sim: An Extensible Simulation Framework for Validated GPU Modeling
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A Case for Hardware-Based Demand Paging
inferred← citeshttps://doi.org/10.1109/isca52012.2021.00054openalex-snapshot
Large-Scale Graph Processing on FPGAs with Caches for Thousands of Simultaneous Misses
inferred← citeshttps://doi.org/10.1109/ispass.2009.4919648openalex-snapshot
Analyzing CUDA workloads using a detailed GPU simulator
inferred← citeshttps://doi.org/10.1109/ispaw.2011.56openalex-snapshot
Evaluating the Memory System Performance of Software-Initiated Inter-core LLC Prepushing
inferred← citeshttps://doi.org/10.1109/ispdc.2010.16openalex-snapshot
Resource-Aware Compiler Prefetching for Many-Cores
inferred← citeshttps://doi.org/10.1109/micro.2008.4771779openalex-snapshot
Hybrid analytical modeling of pending cache hits, data prefetching, and MSHRs
inferred← citeshttps://doi.org/10.1109/nas.2019.8834726openalex-snapshot
HCMA: Supporting High Concurrency of Memory Accesses with Scratchpad Memory in FPGAs
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A Connection Oriented Framework for Effectively Using Multicore in the Enterprise
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Taming Non-Blocking Caches to Improve Isolation in Multicore Real-Time Systems
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On-Chip Network Evaluation Framework
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CaL: Extending Data Locality to Consider Concurrency for Performance Optimization
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RAMON: Region-Aware Memory Controller
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Architectural Impacts of RFiop: RF to Address I/O Pad and Memory Controller Scalability
inferred← citeshttps://doi.org/10.1109/tvlsi.2023.3326741openalex-snapshot
TensorCache: Reconstructing Memory Architecture With SRAM-Based In-Cache Computing for Efficient Tensor Computations in GPGPUs
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3D-Stacked Memory Architectures for Multi-core Processors
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Complexity effective memory access scheduling for many-core accelerator architectures
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Improving memory bank-level parallelism in the presence of prefetching
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A practical way to extend shared memory support beyond a motherboard at low cost
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Hybrid analytical modeling of pending cache hits, data prefetching, and MSHRs
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Mixed speculative multithreaded execution models
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Heterogeneous system coherence for integrated CPU-GPU systems
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Measuring Microarchitectural Details of Multi- and Many-Core Memory Systems through Microbenchmarking
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Page Placement Strategies for GPUs within Heterogeneous Memory Systems
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Page Placement Strategies for GPUs within Heterogeneous Memory Systems
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Page Placement Strategies for GPUs within Heterogeneous Memory Systems
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Memory Coalescing for Hybrid Memory Cube
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Stop Crying Over Your Cache Miss Rate
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Demystifying Complex Workload-DRAM Interactions
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Dynamically linked MSHRs for adaptive miss handling in GPUs
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inferred← citeshttps://doi.org/10.1145/3626202.3637571openalex-snapshot
MiCache: An MSHR-inclusive Non-blocking Cache Design for FPGAs
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