On the public citation graph

A scalable processing-in-memory accelerator for parallel graph processing

0 signed · 808 inferred · view as graph

Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.

Is this your work? Sign in with ORCID and put your name on the claims that are yours.

Claim with ORCID

Reference health. See whether every reference in this work resolves to a known work and none has been retracted — and get a dated CiteStamped badge you can embed.

See reference health

What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/978-3-540-77220-0_21openalex-snapshot

Accelerating Large Graph Algorithms on the GPU Using CUDA

inferredcites →https://doi.org/10.1016/j.jpdc.2004.11.004openalex-snapshot

Memory-side prefetching for linked data structures for processor-in-memory systems

inferredcites →https://doi.org/10.1016/s0169-7552(98)00110-xopenalex-snapshot

The anatomy of a large-scale hypertextual Web search engine

inferredcites →https://doi.org/10.1109/12.381947openalex-snapshot

Effective hardware-based data prefetching for high-performance processors

inferredcites →https://doi.org/10.1109/2.375174openalex-snapshot

Processing in memory: the Terasys massively parallel PIM array

inferredcites →https://doi.org/10.1109/3dic.2013.6702348openalex-snapshot

A 3D-stacked logic-in-memory accelerator for application-specific data intensive computing

inferredcites →https://doi.org/10.1109/99.660313openalex-snapshot

OpenMP: an industry standard API for shared-memory programming

inferredcites →https://doi.org/10.1109/hpca.2003.1183532openalex-snapshot

Runahead execution: an alternative to very large instruction windows for out-of-order processors

inferredcites →https://doi.org/10.1109/hpca.2007.346185openalex-snapshot

Feedback Directed Prefetching: Improving the Performance and Bandwidth-Efficiency of Hardware Prefetchers

inferredcites →https://doi.org/10.1109/hpec.2013.6670336openalex-snapshot

Accelerating sparse matrix-matrix multiplication with 3D-stacked logic-in-memory hardware

inferredcites →https://doi.org/10.1109/iccd.2012.6378608openalex-snapshot

FlexRAM: Toward an advanced Intelligent Memory system

inferredcites →https://doi.org/10.1109/icpp.1994.108openalex-snapshot

EXECUBE-A New Architecture for Scaleable MPPs

inferredcites →https://doi.org/10.1109/isca.2008.15openalex-snapshot

3D-Stacked Memory Architectures for Multi-core Processors

inferredcites →https://doi.org/10.1109/ispass.2014.6844483openalex-snapshot

NDC: Analyzing the impact of 3D-stacked memory+logic devices on MapReduce workloads

inferredcites →https://doi.org/10.1109/isscc.1997.585348openalex-snapshot

Intelligent RAM (IRAM): chips that remember and compute

inferredcites →https://doi.org/10.1109/mc.2011.18openalex-snapshot

From Microprocessors to Nanostores: Rethinking Data-Centric Systems

inferredcites →https://doi.org/10.1109/mm.2014.55openalex-snapshot

Near-Data Processing: Insights from a MICRO-46 Workshop

inferredcites →https://doi.org/10.1109/pact.2011.14openalex-snapshot

Efficient Parallel Graph Exploration on Multi-Core CPU and GPU

inferredcites →https://doi.org/10.1109/pact.2013.6618812openalex-snapshot

Memory-centric system interconnect design with Hybrid Memory Cubes

inferredcites →https://doi.org/10.1109/vlsit.2012.6242474openalex-snapshot

Hybrid memory cube new DRAM architecture increases density and performance

inferredcites →https://doi.org/10.1137/s1064827595287997openalex-snapshot

A Fast and High Quality Multilevel Scheme for Partitioning Irregular Graphs

inferredcites →https://doi.org/10.1145/1064978.1065034openalex-snapshot

inferredcites →https://doi.org/10.1145/1065010.1065034openalex-snapshot

inferredcites →https://doi.org/10.1145/1168857.1168873openalex-snapshot

PicoServer

inferredcites →https://doi.org/10.1145/1298306.1298311openalex-snapshot

Measurement and analysis of online social networks

inferredcites →https://doi.org/10.1145/1394608.1382159openalex-snapshot

3D-Stacked Memory Architectures for Multi-core Processors

inferredcites →https://doi.org/10.1145/1508244.1508274openalex-snapshot

Accelerating critical section execution with asymmetric multi-core architectures

inferredcites →https://doi.org/10.1145/1713254.1713276openalex-snapshot

The case for RAMClouds

inferredcites →https://doi.org/10.1145/1807167.1807184openalex-snapshot

Pregel

inferredcites →https://doi.org/10.1145/1941553.1941590openalex-snapshot

Accelerating CUDA graph algorithms at maximum warp

inferredcites →https://doi.org/10.1145/2080.357392openalex-snapshot

Implementing remote procedure calls

inferredcites →https://doi.org/10.1145/2145816.2145832openalex-snapshot

Scalable GPU graph traversal

inferredcites →https://doi.org/10.1145/2150976.2150982openalex-snapshot

Clearing the clouds

inferredcites →https://doi.org/10.1145/2150976.2151013openalex-snapshot

Green-Marl

inferredcites →https://doi.org/10.1145/2484838.2484843openalex-snapshot

GPS

inferredcites →https://doi.org/10.1145/2485922.2485925openalex-snapshot

Convolution engine

inferredcites →https://doi.org/10.1145/2485922.2485926openalex-snapshot

Thin servers with smart pipes

inferredcites →https://doi.org/10.1145/2485922.2485943openalex-snapshot

Efficient virtual memory for big memory servers

inferredcites →https://doi.org/10.1145/2485922.2485944openalex-snapshot

Navigating big data with high-throughput, energy-efficient data partitioning

inferredcites →https://doi.org/10.1145/2485922.2485945openalex-snapshot

LINQits

inferredcites →https://doi.org/10.1145/2540708.2540725openalex-snapshot

RowClone

inferredcites →https://doi.org/10.1145/2540708.2540726openalex-snapshot

Quantifying the relationship between the power delivery network and architectural policies in a 3D-stacked memory device

inferredcites →https://doi.org/10.1145/2540708.2540748openalex-snapshot

Meet the walkers

inferredcites →https://doi.org/10.1145/2541940.2541951openalex-snapshot

Integrated 3D-stacked server designs for increasing physical density of key-value stores

inferredcites →https://doi.org/10.1145/2544137.2544162openalex-snapshot

Simplifying Scalable Graph Processing with a Domain-Specific Language

inferredcites →https://doi.org/10.1145/2581122.2544162openalex-snapshot

Simplifying Scalable Graph Processing with a Domain-Specific Language

inferredcites →https://doi.org/10.1145/2600212.2600213openalex-snapshot

TOP-PIM

inferredcites →https://doi.org/10.1145/2628071.2628091openalex-snapshot

KLA

inferredcites →https://doi.org/10.1145/279358.279387openalex-snapshot

Active pages: a computation model for intelligent memory

inferredcites →https://doi.org/10.1145/285930.285979openalex-snapshot

Lockup-free instruction fetch/prefetch cache organization

inferredcites →https://doi.org/10.1145/285930.285998openalex-snapshot

Improving direct-mapped cache performance by the addition of a small fully-associative cache prefetch buffers

inferredcites →https://doi.org/10.1145/325164.325162openalex-snapshot

Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers

inferredcites →https://doi.org/10.1145/331532.331589openalex-snapshot

Mapping irregular applications to DIVA, a PIM-based data-intensive architecture

inferredcites →https://doi.org/10.1145/335231.335248openalex-snapshot

Push vs. pull

inferredcites →https://doi.org/10.1145/545214.545235openalex-snapshot

Using a user-level memory thread for correlation prefetching

inferredcites →https://doi.org/10.14778/2212351.2212354openalex-snapshot

Distributed GraphLab

inferredcites →https://doi.org/10.14778/2732232.2732238openalex-snapshot

From "think like a vertex" to "think like a graph"

inferredcites →https://doi.org/10.5555/2387880.2387883openalex-snapshot

PowerGraph: distributed graph-parallel computation on natural graphs

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.2139/ssrn.4007736openalex-extracted

inferred← citeshttps://doi.org/10.5281/zenodo.21082396zenodo-depositor-declared

inferred← citeshttps://doi.org/10.5281/zenodo.6942162openalex-extracted

inferred← citeshttps://doi.org/10.1002/047134608x.w8438openalex-snapshot

Emerging Memory Structures for VLSI Circuits

inferred← citeshttps://doi.org/10.1002/9781119813873.ch9openalex-snapshot

The Road Ahead

inferred← citeshttps://doi.org/10.1002/cpe.4064openalex-snapshot

Efficient and high‐quality sparse graph coloring on GPUs

inferred← citeshttps://doi.org/10.1007/978-3-030-20656-7_5openalex-snapshot

A Near-Data Processing Server Architecture and Its Impact on Data Center Applications

inferred← citeshttps://doi.org/10.1007/978-3-030-32813-9_16openalex-snapshot

Power Characterization of Memory Intensive Applications: Analysis and Implications

inferred← citeshttps://doi.org/10.1007/978-3-030-37224-8_6openalex-snapshot

Near-Memory/In-Memory Computing: Pillars and Ladders

inferred← citeshttps://doi.org/10.1007/978-3-030-52794-5_9openalex-snapshot

X-CEL: A Method to Estimate Near-Memory Acceleration Potential in Tile-Based MPSoCs

inferred← citeshttps://doi.org/10.1007/978-3-030-59016-1_24openalex-snapshot

Optimizing Motion Estimation with an ReRAM-Based PIM Architecture

inferred← citeshttps://doi.org/10.1007/978-3-030-98781-7_7openalex-snapshot

PIM Software Stack

inferred← citeshttps://doi.org/10.1007/978-3-031-12597-3_18openalex-snapshot

GraphGuess: Approximate Graph Processing System with Adaptive Correction

inferred← citeshttps://doi.org/10.1007/978-3-031-19568-6_10openalex-snapshot

Using Approximate DRAM for Enabling Energy-Efficient, High-Performance Deep Neural Network Inference

inferred← citeshttps://doi.org/10.1007/978-3-031-22677-9_19openalex-snapshot

MatGraph: An Energy-Efficient and Flexible CGRA Engine for Matrix-Based Graph Analytics

inferred← citeshttps://doi.org/10.1007/978-3-031-34214-1_5openalex-snapshot

Exploiting Heterogeneity in PIM Architectures for Data-Intensive Applications

inferred← citeshttps://doi.org/10.1007/978-3-031-42785-5_18openalex-snapshot

Optimization of OLAP In-Memory Database Management Systems with Processing-In-Memory Architecture

inferred← citeshttps://doi.org/10.1007/978-3-031-46077-7_30openalex-snapshot

A Case for Genome Analysis Where Genomes Reside

inferred← citeshttps://doi.org/10.1007/978-3-031-85697-6_6openalex-snapshot

Exploring the Design Space for Message-Driven Systems for Dynamic Graph Processing Using CCA

inferred← citeshttps://doi.org/10.1007/978-3-032-07001-2_20openalex-snapshot

The Computing Genome Is a Logical Vector

inferred← citeshttps://doi.org/10.1007/978-3-319-30695-7_2openalex-snapshot

Design and Evaluation of a Processing-in-Memory Architecture for the Smart Memory Cube

inferred← citeshttps://doi.org/10.1007/978-3-319-54313-0_10openalex-snapshot

Processing-In-Memory Architecture Design for Accelerating Neuro-Inspired Algorithms

inferred← citeshttps://doi.org/10.1007/978-3-319-54999-6_17openalex-snapshot

DVFS Space Exploration in Power Constrained Processing-in-Memory Systems

inferred← citeshttps://doi.org/10.1007/978-3-319-90385-9_5openalex-snapshot

The Processing-in-Memory Paradigm: Mechanisms to Enable Adoption

inferred← citeshttps://doi.org/10.1007/978-981-13-8379-3_9openalex-snapshot

Spintronic Logic-in-Memory Paradigms and Implementations

inferred← citeshttps://doi.org/10.1007/978-981-15-8135-9_6openalex-snapshot

GNN-PIM: A Processing-in-Memory Architecture for Graph Neural Networks

inferred← citeshttps://doi.org/10.1007/978-981-16-7487-7_7openalex-snapshot

A Modern Primer on Processing in Memory

inferred← citeshttps://doi.org/10.1007/978-981-19-1012-8_36openalex-snapshot

Barriers to the Widespread Adoption of Processing-in-Memory Architectures

inferred← citeshttps://doi.org/10.1007/978-981-19-7636-0_4openalex-snapshot

Current Application Fields

inferred← citeshttps://doi.org/10.1007/978-981-95-8337-9_50openalex-snapshot

Accelerating Transformer Fault Diagnosis Method Based on Data and Mechanism

inferred← citeshttps://doi.org/10.1007/978-981-95-8399-7_28openalex-snapshot

HT-DLC: A Data Layout and Computing Design for Logic-in-Memory Convolution with High Throughput

inferred← citeshttps://doi.org/10.1007/978-981-99-4764-5_18openalex-snapshot

An HBM3 Processing-In-Memory Architecture for Security and Data Integrity: Case Study

inferred← citeshttps://doi.org/10.1007/s00778-025-00937-5openalex-snapshot

PIM-tree: A Skew-resistant Index for Processing-in-Memory

inferred← citeshttps://doi.org/10.1007/s10766-020-00674-yopenalex-snapshot

Enabling Near-Data Accelerators Adoption by Through Investigation of Datapath Solutions

inferred← citeshttps://doi.org/10.1007/s11227-018-2589-xopenalex-snapshot

Accelerated bulk memory operations on heterogeneous multi-core systems

inferred← citeshttps://doi.org/10.1007/s11227-021-03661-3openalex-snapshot

Enabling fast and energy-efficient FM-index exact matching using processing-near-memory

inferred← citeshttps://doi.org/10.1007/s11227-026-08883-xopenalex-snapshot

Accelerating dynamic graph computation via space-aware mapping approach in computing-in-memory systems

inferred← citeshttps://doi.org/10.1007/s11265-025-01974-7openalex-snapshot

An Experimental Exploration of In-Memory Computing for Multi-Layer Perceptrons

inferred← citeshttps://doi.org/10.1007/s11390-019-1914-zopenalex-snapshot

A Survey on Graph Processing Accelerators: Challenges and Opportunities

inferred← citeshttps://doi.org/10.1007/s11390-020-0825-3openalex-snapshot

PIM-Align: A Processing-in-Memory Architecture for FM-Index Search Algorithm

inferred← citeshttps://doi.org/10.1007/s11390-021-1242-yopenalex-snapshot

FDGLib: A Communication Library for Efficient Large-Scale Graph Processing in FPGA-Accelerated Data Centers

inferred← citeshttps://doi.org/10.1007/s11432-020-3189-xopenalex-snapshot

Stateful implication logic based on perpendicular magnetic tunnel junctions

inferred← citeshttps://doi.org/10.1007/s11432-020-3219-6openalex-snapshot

Graph processing and machine learning architectures with emerging memory technologies: a survey

inferred← citeshttps://doi.org/10.1007/s11432-020-3227-1openalex-snapshot

Breaking the von Neumann bottleneck: architecture-level processing-in-memory technology

inferred← citeshttps://doi.org/10.1007/s11432-021-3234-0openalex-snapshot

Energy-efficient computing-in-memory architecture for AI processor: device, circuit, architecture perspective

inferred← citeshttps://doi.org/10.1007/s11704-019-9020-5openalex-snapshot

Efficient FPGA-based graph processing with hybrid pull-push computational model

inferred← citeshttps://doi.org/10.1007/s13222-017-0255-8openalex-snapshot

Big Graph Data Analytics on Single Machines – An Overview

inferred← citeshttps://doi.org/10.1007/s41939-024-00517-0openalex-snapshot

In-memory computing: characteristics, spintronics, and neural network applications insights

inferred← citeshttps://doi.org/10.1007/s42514-020-00041-wopenalex-snapshot

Effective runtime scheduling for high-performance graph processing on heterogeneous dataflow architecture

inferred← citeshttps://doi.org/10.1007/s42979-022-01165-2openalex-snapshot

Fast Sobel Edge Detection for IoT Edge Devices

inferred← citeshttps://doi.org/10.1007/s44443-026-01039-0openalex-snapshot

HyST-DNA: Hybrid SRAM-TCAM DNN accelerator with genetic optimization on FPGA

inferred← citeshttps://doi.org/10.1016/b978-0-12-805394-2.00006-4openalex-snapshot

Database Techniques for Big Data

inferred← citeshttps://doi.org/10.1016/bs.adcom.2017.04.004openalex-snapshot

Simple Operations in Memory to Reduce Data Movement

inferred← citeshttps://doi.org/10.1016/bs.adcom.2018.03.001openalex-snapshot

Dark Silicon and the History of Computing

inferred← citeshttps://doi.org/10.1016/bs.adcom.2018.03.009openalex-snapshot

Topology Specialization for Networks-on-Chip in the Dark Silicon Era

inferred← citeshttps://doi.org/10.1016/bs.adcom.2021.12.002openalex-snapshot

The design of an energy-efficient deflection-based on-chip network

inferred← citeshttps://doi.org/10.1016/j.future.2017.12.033openalex-snapshot

In-memory big data analytics under space constraints using dynamic programming

inferred← citeshttps://doi.org/10.1016/j.future.2020.03.015openalex-snapshot

Access pattern-based high-performance main memory system for graph processing on single machines

inferred← citeshttps://doi.org/10.1016/j.jpdc.2019.04.011openalex-snapshot

Collaborative Compaction Optimization System using Near-Data Processing for LSM-tree-based Key-Value Stores

inferred← citeshttps://doi.org/10.1016/j.jpdc.2021.10.009openalex-snapshot

A hardware/software co-design methodology for in-memory processors

inferred← citeshttps://doi.org/10.1016/j.mejo.2018.09.005openalex-snapshot

A high-reliability and low-power computing-in-memory implementation within STT-MRAM

inferred← citeshttps://doi.org/10.1016/j.mejo.2019.104637openalex-snapshot

Enhanced graph processing in PIM accelerators with improved queue management

inferred← citeshttps://doi.org/10.1016/j.micpro.2017.01.005openalex-snapshot

Optimizing power efficiency for 3D stacked GPU-in-memory architecture

inferred← citeshttps://doi.org/10.1016/j.micpro.2019.01.009openalex-snapshot

Processing data where it makes sense: Enabling in-memory computation

inferred← citeshttps://doi.org/10.1016/j.micpro.2019.06.002openalex-snapshot

A Technologically Agnostic Framework for Cyber-Physical and IoT Processing-in-Memory-based Systems Simulation

inferred← citeshttps://doi.org/10.1016/j.micpro.2019.102868openalex-snapshot

Near-memory computing: Past, present, and future

inferred← citeshttps://doi.org/10.1016/j.micpro.2022.104707openalex-snapshot

NDP-RANK: Prediction and ranking of NDP systems performance using machine learning

inferred← citeshttps://doi.org/10.1016/j.neunet.2024.106312openalex-snapshot

A memristive all-inclusive hypernetwork for parallel analog deployment of full search space architectures

inferred← citeshttps://doi.org/10.1016/j.parco.2023.103017openalex-snapshot

A heterogeneous processing-in-memory approach to accelerate quantum chemistry simulation

inferred← citeshttps://doi.org/10.1016/j.suscom.2019.01.006openalex-snapshot

PIM-WEAVER: A High Energy-efficient, General-purpose Acceleration Architecture for String Operations in Big Data Processing

inferred← citeshttps://doi.org/10.1016/j.suscom.2020.100465openalex-snapshot

Energy characterization of graph workloads

inferred← citeshttps://doi.org/10.1016/j.sysarc.2019.06.007openalex-snapshot

LG-RAM: Load-aware global resource affinity management for virtualized multicore systems

inferred← citeshttps://doi.org/10.1016/j.sysarc.2021.102123openalex-snapshot

An efficient highly parallelized ReRAM-based architecture for motion estimation of HEVC

inferred← citeshttps://doi.org/10.1016/j.sysarc.2022.102602openalex-snapshot

G-NMP: Accelerating Graph Neural Networks with DIMM-based Near-Memory Processing

inferred← citeshttps://doi.org/10.1016/j.sysarc.2022.102755openalex-snapshot

GraphA: An efficient ReRAM-based architecture to accelerate large scale graph processing

inferred← citeshttps://doi.org/10.1016/j.vlsi.2019.02.007openalex-snapshot

Exploiting the Logic-In-Memory paradigm for speeding-up data-intensive algorithms

inferred← citeshttps://doi.org/10.1016/j.vlsi.2022.09.016openalex-snapshot

Plug N’ PIM: An integration strategy for Processing-in-Memory accelerators

inferred← citeshttps://doi.org/10.1021/acsomega.3c05352openalex-snapshot

Wide-Range Synaptic Current Responses with a Liquid Ga Electrode via a Surface Redox Reaction in a NaOH Solution at Different Molar Concentrations

inferred← citeshttps://doi.org/10.1049/iet-cdt.2019.0092openalex-snapshot

Survey on memory management techniques in heterogeneous computing systems

inferred← citeshttps://doi.org/10.1088/1742-6596/1914/1/012023openalex-snapshot

LooPIM: A Loop-Oriented Acceleration Framework for Processing-in-Memory

inferred← citeshttps://doi.org/10.1093/nsr/nwx082openalex-snapshot

Memory that never forgets: emerging nonvolatile memory and the implication for architecture design

inferred← citeshttps://doi.org/10.1109/access.2018.2873579openalex-snapshot

DStore: A Holistic Key-Value Store Exploring Near-Data Processing and On-Demand Scheduling for Compaction Optimization

inferred← citeshttps://doi.org/10.1109/access.2019.2924240openalex-snapshot

Design of Processing-“Inside”-Memory Optimized for DRAM Behaviors

inferred← citeshttps://doi.org/10.1109/access.2020.3003982openalex-snapshot

ReGra: Accelerating Graph Traversal Applications Using ReRAM With Lower Communication Cost

inferred← citeshttps://doi.org/10.1109/access.2020.3008250openalex-snapshot

Hardware-Accelerated Platforms and Infrastructures for Network Functions: A Survey of Enabling Technologies and Research Studies

inferred← citeshttps://doi.org/10.1109/access.2021.3077294openalex-snapshot

Task Parallelism-Aware Deep Neural Network Scheduling on Multiple Hybrid Memory Cube-Based Processing-in-Memory

inferred← citeshttps://doi.org/10.1109/access.2021.3110993openalex-snapshot

DAMOV: A New Methodology and Benchmark Suite for Evaluating Data Movement Bottlenecks

inferred← citeshttps://doi.org/10.1109/access.2021.3122818openalex-snapshot

Functionality-Based Processing-in-Memory Accelerator for Deep Convolutional Neural Networks

inferred← citeshttps://doi.org/10.1109/access.2022.3174101openalex-snapshot

Benchmarking a New Paradigm: Experimental Analysis and Characterization of a Real Processing-in-Memory System

inferred← citeshttps://doi.org/10.1109/access.2024.3450105openalex-snapshot

Beyond Von Neumann Architectures: Exploring Algorithmic Opportunities via Octantis

inferred← citeshttps://doi.org/10.1109/access.2024.3486297openalex-snapshot

Advanced Integration-Inspired Process-in-Memory: A Comprehensive Review of Design, Challenges, and Future Prospects

inferred← citeshttps://doi.org/10.1109/access.2024.3514377openalex-snapshot

Rethinking the Producer-Consumer Relationship in Modern DRAM-Based Systems

inferred← citeshttps://doi.org/10.1109/access.2025.3548572openalex-snapshot

Development of In-Memory Computing Device Using Positive Feedback Field Effect Transistor Based on NAND Flash Array

inferred← citeshttps://doi.org/10.1109/acsac67867.2025.00083openalex-snapshot

PIM-ORAM: Towards Oblivious RAM Primitives in Commodity Processing-In-Memory

inferred← citeshttps://doi.org/10.1109/apccas.2016.7804052openalex-snapshot

PIM architecture exploration for HMC

inferred← citeshttps://doi.org/10.1109/asap.2018.8445124openalex-snapshot

A Customized Processing-in-Memory Architecture for Biological Sequence Alignment

inferred← citeshttps://doi.org/10.1109/asap57973.2023.00035openalex-snapshot

SieveMem: A Computation-in-Memory Architecture for Fast and Accurate Pre-Alignment

inferred← citeshttps://doi.org/10.1109/asp-dac52403.2022.9712502openalex-snapshot

Computation-in-Memory Accelerators for Secure Graph Database: Opportunities and Challenges

inferred← citeshttps://doi.org/10.1109/asp-dac52403.2022.9712587openalex-snapshot

Optimal Data Allocation for Graph Processing in Processing-in-Memory Systems

inferred← citeshttps://doi.org/10.1109/aspdac.2017.7858355openalex-snapshot

ApproxPIM: Exploiting realistic 3D-stacked DRAM for energy-efficient processing in-memory

inferred← citeshttps://doi.org/10.1109/aspdac.2017.7858412openalex-snapshot

BoDNoC: Providing bandwidth-on-demand interconnection for multi-granularity memory systems

inferred← citeshttps://doi.org/10.1109/aspdac.2018.8297307openalex-snapshot

PIMCH: Cooperative memory prefetching in processing-in-memory architecture

inferred← citeshttps://doi.org/10.1109/aspdac.2018.8297348openalex-snapshot

XORiM: A case of in-memory bit-comparator implementation and its performance implications

inferred← citeshttps://doi.org/10.1109/bigdata.2015.7363861openalex-snapshot

Early experience with optimizing I/O performance using high-performance SSDs for in-memory cluster computing

inferred← citeshttps://doi.org/10.1109/bigdata.2016.7840840openalex-snapshot

Fine-grained power analysis of emerging graph processing workloads for cloud operations management

inferred← citeshttps://doi.org/10.1109/ccgrid.2017.114openalex-snapshot

TuNao: A High-Performance and Energy-Efficient Reconfigurable Accelerator for Graph Processing

inferred← citeshttps://doi.org/10.1109/ccmcc67628.2025.11380453openalex-snapshot

CryptoSRAM: Enabling High-Throughput Cryptography on MCUs via In-SRAM Computing

inferred← citeshttps://doi.org/10.1109/cgo.2017.7863729openalex-snapshot

Dynamic buffer overflow detection for GPGPUs

inferred← citeshttps://doi.org/10.1109/ciss.2017.7926139openalex-snapshot

Energy-reliability limits in nanoscale neural networks

inferred← citeshttps://doi.org/10.1109/cluster.2017.44openalex-snapshot

OmniGraph: A Scalable Hardware Accelerator for Graph Processing

inferred← citeshttps://doi.org/10.1109/cluster48925.2021.00049openalex-snapshot

Two-Chains: High Performance Framework for Function Injection and Execution

inferred← citeshttps://doi.org/10.1109/cstic.2018.8369328openalex-snapshot

An accelerator-aware microarchitecture simulator for design space exploration

inferred← citeshttps://doi.org/10.1109/dac.2018.8465822openalex-snapshot

Employing Classification-based Algorithms for General-Purpose Approximate Computing

inferred← citeshttps://doi.org/10.1109/dac18072.2020.9218624openalex-snapshot

Centaur: Hybrid Processing in On/Off-chip Memory Architecture for Graph Analytics

inferred← citeshttps://doi.org/10.1109/dac18072.2020.9218638openalex-snapshot

PattPIM: A Practical ReRAM-Based DNN Accelerator by Reusing Weight Pattern Repetitions

inferred← citeshttps://doi.org/10.1109/dac18074.2021.9586122openalex-snapshot

GNNerator: A Hardware/Software Framework for Accelerating Graph Neural Networks

inferred← citeshttps://doi.org/10.1109/dac18074.2021.9586212openalex-snapshot

MAT: Processing In-Memory Acceleration for Long-Sequence Attention

inferred← citeshttps://doi.org/10.1109/dac56929.2023.10247745openalex-snapshot

vPIM: Efficient Virtual Address Translation for Scalable Processing-in-Memory Architectures

inferred← citeshttps://doi.org/10.1109/dac56929.2023.10247896openalex-snapshot

Lightning Talk: Memory-Centric Computing

inferred← citeshttps://doi.org/10.1109/dac63849.2025.11133299openalex-snapshot

NDFT: Accelerating Density Functional Theory Calculations via Hardware/Software Co-Design on Near-Data Computing System

inferred← citeshttps://doi.org/10.1109/dac63849.2025.11133391openalex-snapshot

PIMPAL: Accelerating LLM Inference on Edge Devices via In-DRAM Arithmetic Lookup

inferred← citeshttps://doi.org/10.1109/dcas69364.2026.11544917openalex-snapshot

Vulnerability Analysis of Timing Side-Channels in Multi-Tenant ReRAM Crossbars

inferred← citeshttps://doi.org/10.1109/dsd.2018.00106openalex-snapshot

A Review of Near-Memory Computing Architectures: Opportunities and Challenges

inferred← citeshttps://doi.org/10.1109/dsd.2019.00093openalex-snapshot

Platform Independent Software Analysis for Near Memory Computing

inferred← citeshttps://doi.org/10.1109/dsd53832.2021.00033openalex-snapshot

Near-Data-Processing Architectures Performance Estimation and Ranking using Machine Learning Predictors

inferred← citeshttps://doi.org/10.1109/edge60047.2023.00018openalex-snapshot

Spica: Exploring FPGA Optimizations to Enable an Efficient SpMV Implementation for Computations at Edge

inferred← citeshttps://doi.org/10.1109/eurosime52062.2021.9410836openalex-snapshot

Thermal Analysis of Microfluidic cooling in Processing-in-3D-Stacked Memory

inferred← citeshttps://doi.org/10.1109/fccm60383.2024.00027openalex-snapshot

MPC-Wrapper: Fully Harnessing the Potential of Samsung Aquabolt-XL HBM2-PIM on FPGAs

inferred← citeshttps://doi.org/10.1109/fpl50879.2020.00014openalex-snapshot

NERO: A Near High-Bandwidth Memory Stencil Accelerator for Weather Prediction Modeling

inferred← citeshttps://doi.org/10.1109/hotchips.2014.7478840openalex-snapshot

Memory processing units

inferred← citeshttps://doi.org/10.1109/hpca.2016.7446059openalex-snapshot

HRL: Efficient and flexible reconfigurable logic for near-data processing

inferred← citeshttps://doi.org/10.1109/hpca.2017.37openalex-snapshot

Processing-in-Memory Enabled Graphics Processors for 3D Rendering

inferred← citeshttps://doi.org/10.1109/hpca.2017.54openalex-snapshot

GraphPIM: Enabling Instruction-Level PIM Offloading in Graph Computing Frameworks

inferred← citeshttps://doi.org/10.1109/hpca.2017.55openalex-snapshot

PipeLayer: A Pipelined ReRAM-Based Accelerator for Deep Learning

inferred← citeshttps://doi.org/10.1109/hpca.2018.00052openalex-snapshot

GraphR: Accelerating Graph Processing Using ReRAM

inferred← citeshttps://doi.org/10.1109/hpca.2018.00053openalex-snapshot

GraphP: Reducing Communication for PIM-Based Graph Processing with Efficient Data Partition

inferred← citeshttps://doi.org/10.1109/hpca.2018.00054openalex-snapshot

PM3: Power Modeling and Power Management for Processing-in-Memory

inferred← citeshttps://doi.org/10.1109/hpca.2019.00011openalex-snapshot

D-RaNGe: Using Commodity DRAM Devices to Generate True Random Numbers with Low Latency and High Throughput

inferred← citeshttps://doi.org/10.1109/hpca.2019.00013openalex-snapshot

PIM-VR: Erasing Motion Anomalies In Highly-Interactive Virtual Reality World with Customized Memory Cube

inferred← citeshttps://doi.org/10.1109/hpca.2019.00018openalex-snapshot

Active-Routing: Compute on the Way for Near-Data Processing

inferred← citeshttps://doi.org/10.1109/hpca.2019.00042openalex-snapshot

Architecting Waferscale Processors - A GPU Case Study

inferred← citeshttps://doi.org/10.1109/hpca.2019.00051openalex-snapshot

Analysis and Optimization of the Memory Hierarchy for Graph Processing Workloads

inferred← citeshttps://doi.org/10.1109/hpca47549.2020.00011openalex-snapshot

Deep Learning Acceleration with Neuron-to-Memory Transformation

inferred← citeshttps://doi.org/10.1109/hpca47549.2020.00029openalex-snapshot

ALRESCHA: A Lightweight Reconfigurable Sparse-Computation Accelerator

inferred← citeshttps://doi.org/10.1109/hpca47549.2020.00051openalex-snapshot

Enabling Highly Efficient Capsule Networks Processing Through A PIM-Based Architecture Design

inferred← citeshttps://doi.org/10.1109/hpca47549.2020.00059openalex-snapshot

Hybrid2: Combining Caching and Migration in Hybrid Memory Systems

inferred← citeshttps://doi.org/10.1109/hpca51647.2021.00030openalex-snapshot

GradPIM: A Practical Processing-in-DRAM Architecture for Gradient Descent

inferred← citeshttps://doi.org/10.1109/hpca51647.2021.00031openalex-snapshot

SynCron: Efficient Synchronization Support for Near-Data-Processing Architectures

inferred← citeshttps://doi.org/10.1109/hpca51647.2021.00045openalex-snapshot

Memristive Data Ranking

inferred← citeshttps://doi.org/10.1109/hpca51647.2021.00055openalex-snapshot

SpaceA: Sparse Matrix Vector Multiplication on Processing-in-Memory Accelerator

inferred← citeshttps://doi.org/10.1109/hpca51647.2021.00061openalex-snapshot

Prodigy: Improving the Memory Latency of Data-Indirect Irregular Workloads Using Hardware-Software Co-Design

inferred← citeshttps://doi.org/10.1109/hpca51647.2021.00080openalex-snapshot

FAFNIR: Accelerating Sparse Gathering by Using Efficient Near-Memory Intelligent Reduction

inferred← citeshttps://doi.org/10.1109/hpca53966.2022.00026openalex-snapshot

SecNDP: Secure Near-Data Processing with Untrusted Memory

inferred← citeshttps://doi.org/10.1109/hpca53966.2022.00032openalex-snapshot

Near-Stream Computing: General and Transparent Near-Cache Acceleration

inferred← citeshttps://doi.org/10.1109/hpca53966.2022.00082openalex-snapshot

TransPIM: A Memory-based Acceleration via Software-Hardware Co-Design for Transformer

inferred← citeshttps://doi.org/10.1109/hpca53966.2022.00083openalex-snapshot

PIMCloud: QoS-Aware Resource Management of Latency-Critical Applications in Clouds with Processing-in-Memory

inferred← citeshttps://doi.org/10.1109/hpca53966.2022.00087openalex-snapshot

DR-STRaNGe: End-to-End System Design for DRAM-based True Random Number Generators

inferred← citeshttps://doi.org/10.1109/hpca56546.2023.10071005openalex-snapshot

DIMM-Link: Enabling Efficient Inter-DIMM Communication for Near-Memory Processing

inferred← citeshttps://doi.org/10.1109/hpca56546.2023.10071074openalex-snapshot

EVE: Ephemeral Vector Engines

inferred← citeshttps://doi.org/10.1109/hpca56546.2023.10071089openalex-snapshot

Dalorex: A Data-Local Program Execution and Architecture for Memory-bound Applications

inferred← citeshttps://doi.org/10.1109/hpca57654.2024.00029openalex-snapshot

Pathfinding Future PIM Architectures by Demystifying a Commercial PIM Technology

inferred← citeshttps://doi.org/10.1109/hpca57654.2024.00040openalex-snapshot

Differential-Matching Prefetcher for Indirect Memory Access

inferred← citeshttps://doi.org/10.1109/hpca57654.2024.00046openalex-snapshot

A Two Level Neural Approach Combining Off-Chip Prediction with Adaptive Prefetch Filtering

inferred← citeshttps://doi.org/10.1109/hpca61900.2025.00047openalex-snapshot

AsyncDIMM: Achieving Asynchronous Execution in DIMM-Based Near-Memory Processing

inferred← citeshttps://doi.org/10.1109/hpca61900.2025.00055openalex-snapshot

Piccolo: Large-Scale Graph Processing with Fine-Grained in-Memory Scatter-Gather

inferred← citeshttps://doi.org/10.1109/hpca61900.2025.00072openalex-snapshot

NOVA: A Novel Vertex Management Architecture for Scalable Graph Processing

inferred← citeshttps://doi.org/10.1109/hpca61900.2025.00087openalex-snapshot

FHENDI: A Near-DRAM Accelerator for Compiler-Generated Fully Homomorphic Encryption Applications

inferred← citeshttps://doi.org/10.1109/hpca61900.2025.00116openalex-snapshot

PIMnet: A Domain-Specific Network for Efficient Collective Communication in Scalable PIM

inferred← citeshttps://doi.org/10.1109/hpca61900.2025.00127openalex-snapshot

FACIL: Flexible DRAM Address Mapping for SoC-PIM Cooperative On-device LLM Inference

inferred← citeshttps://doi.org/10.1109/hpca68181.2026.11408437openalex-snapshot

Conduit: Programmer-Transparent Near-Data Processing Using Multiple Compute-Capable Resources in Solid State Drives

inferred← citeshttps://doi.org/10.1109/hpca68181.2026.11408588openalex-snapshot

PIM-Malloc: A Fast and Scalable Dynamic Memory Allocator for Processing-In-Memory (PIM) Architectures

inferred← citeshttps://doi.org/10.1109/hpca68181.2026.11408595openalex-snapshot

CoCoTree: A Computation-Capable Architecture for Collective Communication in Scalable PIM

inferred← citeshttps://doi.org/10.1109/hpcc/smartcity/dss.2018.00119openalex-snapshot

3D-DRAM Performance for Different OpenMP Scheduling Techniques in Multicore Systems

inferred← citeshttps://doi.org/10.1109/hpec.2017.8091070openalex-snapshot

OSCAR: Optimizing SCrAtchpad reuse for graph processing

inferred← citeshttps://doi.org/10.1109/hpec.2018.8547545openalex-snapshot

Exploiting GPU with 3D Stacked Memory to Boost Performance for Data-Intensive Applications

inferred← citeshttps://doi.org/10.1109/hpsc66065.2025.00008openalex-snapshot

Standardized RISC-V Near-Memory Processing: A Scalable Approach to Data-Intensive Workloads

inferred← citeshttps://doi.org/10.1109/ia3.2016.007openalex-snapshot

Highly Scalable Near Memory Processing with Migrating Threads on the Emu System Architecture

inferred← citeshttps://doi.org/10.1109/icasi.2018.8394513openalex-snapshot

Cycle-accelerated simulation for three-dimensional near-data processing system with power, temperature, and latency analysis

inferred← citeshttps://doi.org/10.1109/icassp43922.2022.9746473openalex-snapshot

PYXIS: An Open-Source Performance Dataset Of Sparse Accelerators

inferred← citeshttps://doi.org/10.1109/iccad.2015.7372648openalex-snapshot

Hardware accelerator design for data centers

inferred← citeshttps://doi.org/10.1109/iccad45719.2019.8942102openalex-snapshot

The Impact of Emerging Technologies on Architectures and System-level Management: Invited Paper

inferred← citeshttps://doi.org/10.1109/iccad51958.2021.9643480openalex-snapshot

Massively Parallel Big Data Classification on a Programmable Processing In-Memory Architecture

inferred← citeshttps://doi.org/10.1109/iccad66269.2025.11240646openalex-snapshot

GenomeDPU: A Cost-Effective In-Memory Data Processing Unit for GPU-based Genome Analysis

inferred← citeshttps://doi.org/10.1109/icccs57501.2023.10151335openalex-snapshot

eBFP: A Processing-in-Memory Storage Method with Parallel Computing and Low Latency

inferred← citeshttps://doi.org/10.1109/iccd.2015.7357143openalex-snapshot

Fixed-function hardware sorting accelerators for near data MapReduce execution

inferred← citeshttps://doi.org/10.1109/iccd.2016.7753257openalex-snapshot

Accelerating pointer chasing in 3D-stacked memory: Challenges, mechanisms, evaluation

inferred← citeshttps://doi.org/10.1109/iccd.2017.40openalex-snapshot

Congra: Towards Efficient Processing of Concurrent Graph Queries on Shared-Memory Machines

inferred← citeshttps://doi.org/10.1109/iccd.2018.00035openalex-snapshot

3D Crosspoint Memory as a Parallel Architecture for Computing Network Reachability

inferred← citeshttps://doi.org/10.1109/iccd46524.2019.00077openalex-snapshot

A High-Performance Processing-in-Memory Accelerator for Inline Data Deduplication

inferred← citeshttps://doi.org/10.1109/iccd50377.2020.00035openalex-snapshot

NATSA: A Near-Data Processing Accelerator for Time Series Analysis

inferred← citeshttps://doi.org/10.1109/iccd56317.2022.00056openalex-snapshot

CPR: Crossbar-grain Pruning for an RRAM-based Accelerator with Coordinate-based Weight Mapping

inferred← citeshttps://doi.org/10.1109/icdcs.2017.150openalex-snapshot

Towards Dataflow-Based Graph Accelerator

inferred← citeshttps://doi.org/10.1109/icdcs.2018.00130openalex-snapshot

Computing In-Memory, Revisited

inferred← citeshttps://doi.org/10.1109/icde53745.2022.00270openalex-snapshot

Polynesia: Enabling High-Performance and Energy-Efficient Hybrid Transactional/Analytical Databases with Hardware/Software Co-Design

inferred← citeshttps://doi.org/10.1109/icdsbs69077.2026.11635026openalex-snapshot

AI-Driven Chiplet-First Network-on-Chip and Network-on-Interposer Co-Design for Universal Chiplet Interconnect Express-Based 2.5D Edge Artificial Intelligence Accelerators

inferred← citeshttps://doi.org/10.1109/iceic54506.2022.9748255openalex-snapshot

Study on Processing-in-Memory Technology based on Dataflow Architecture

inferred← citeshttps://doi.org/10.1109/icit45562.2020.9067234openalex-snapshot

Coherency overhead of Processing-in-Memory in the presence of shared data

inferred← citeshttps://doi.org/10.1109/icpics50287.2020.9202052openalex-snapshot

GNP: A Global-Sensitive Mechanism for Near-Data Processing

inferred← citeshttps://doi.org/10.1109/icpp.2017.12openalex-snapshot

Boosting the Efficiency of HPCG and Graph500 with Near-Data Processing

inferred← citeshttps://doi.org/10.1109/icppw.2016.31openalex-snapshot

Performance Implications of Processing-in-Memory Designs on Data-Intensive Applications

showing the first 200 of 750

Editorial review for independent work. ICSAC — the Institute for Complexity Science and Advanced Computing — runs a structured editorial panel for researchers publishing outside journals, and publishes on CiteStamp rails. Submission is free and goes through ORCID: icsacinstitute.org/submit.