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https://doi.org/10.1145/2600212.2600213
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/978-3-540-45167-9_11openalex-snapshot
On Graph Kernels: Hardness Results and Efficient Alternatives
inferredcites →https://doi.org/10.1109/asap.2009.11openalex-snapshot
Improving VLIW Processor Performance Using Three-Dimensional (3D) DRAM Stacking
inferredcites →https://doi.org/10.1109/aspdac.2013.6509675openalex-snapshot
Reevaluating the latency claims of 3D stacked memories
inferredcites →https://doi.org/10.1109/cisis.2007.49openalex-snapshot
Performance Modeling and Prediction of Parallel and Distributed Computing Systems: A Survey of the State of the Art
inferredcites →https://doi.org/10.1109/hotchips.2011.7477494openalex-snapshot
Hybrid memory cube (HMC)
inferredcites →https://doi.org/10.1109/hotchips.2012.7476485openalex-snapshot
AMD Radeon™ HD 7970 with graphics core next (GCN) architecture
inferredcites →https://doi.org/10.1109/hpca.2010.5416628openalex-snapshot
An optimized 3D-stacked memory architecture by exploiting excessive, high-density TSV bandwidth
inferredcites →https://doi.org/10.1109/hpca.2013.6522329openalex-snapshot
Sonic Millip3De: A massively parallel 3D-stacked accelerator for 3D ultrasound
inferredcites →https://doi.org/10.1109/iccd.2012.6378607openalex-snapshot
FlexRAM: Toward an advanced Intelligent Memory system: A retrospective paper
inferredcites →https://doi.org/10.1109/iccd.2012.6378608openalex-snapshot
FlexRAM: Toward an advanced Intelligent Memory system
inferredcites →https://doi.org/10.1109/icdm.2005.132openalex-snapshot
Shortest-Path Kernels on Graphs
inferredcites →https://doi.org/10.1109/iiswc.2009.5306797openalex-snapshot
Rodinia: A benchmark suite for heterogeneous computing
inferredcites →https://doi.org/10.1109/iiswc.2013.6704684openalex-snapshot
Pannotia: Understanding irregular GPGPU graph applications
inferredcites →https://doi.org/10.1109/ipdps.2002.1015506openalex-snapshot
Memory-intensive benchmarks: IRAM vs. cache-based machines
inferredcites →https://doi.org/10.1109/ipdps.2013.121openalex-snapshot
Exascale computing - A fact or a fiction?
inferredcites →https://doi.org/10.1109/isca.2008.15openalex-snapshot
3D-Stacked Memory Architectures for Multi-core Processors
inferredcites →https://doi.org/10.1109/ispass.2007.363733openalex-snapshot
PTLsim: A Cycle Accurate Full System x86-64 Microarchitectural Simulator
inferredcites →https://doi.org/10.1109/ispass.2014.6844457openalex-snapshot
Sources of error in full-system simulation
inferredcites →https://doi.org/10.1109/ispass.2014.6844483openalex-snapshot
NDC: Analyzing the impact of 3D-stacked memory+logic devices on MapReduce workloads
inferredcites →https://doi.org/10.1109/mc.2003.1250880openalex-snapshot
Energy management for commercial servers
inferredcites →https://doi.org/10.1109/micro.2006.18openalex-snapshot
Die Stacking (3D) Microarchitecture
inferredcites →https://doi.org/10.1109/micro.2010.42openalex-snapshot
Understanding the Energy Consumption of Dynamic Random Access Memories
inferredcites →https://doi.org/10.1109/mm.2011.89openalex-snapshot
GPUs and the Future of Parallel Computing
inferredcites →https://doi.org/10.1109/tpds.2014.8openalex-snapshot
An Efficient and Scalable Semiconductor Architecture for Parallel Automata Processing
inferredcites →https://doi.org/10.1109/vdat.2010.5496640openalex-snapshot
The Exascale challenge
inferredcites →https://doi.org/10.1145/1146909.1147160openalex-snapshot
A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy
inferredcites →https://doi.org/10.1145/1168857.1168873openalex-snapshot
PicoServer
inferredcites →https://doi.org/10.1145/1394608.1382159openalex-snapshot
3D-Stacked Memory Architectures for Multi-core Processors
inferredcites →https://doi.org/10.1145/1555754.1555758openalex-snapshot
Architecting phase change memory as a scalable dram alternative
inferredcites →https://doi.org/10.1145/1555754.1555801openalex-snapshot
Scaling the bandwidth wall
inferredcites →https://doi.org/10.1145/1555815.1555758openalex-snapshot
Architecting phase change memory as a scalable dram alternative
inferredcites →https://doi.org/10.1145/1815961.1815983openalex-snapshot
Rethinking DRAM design and organization for energy-constrained multi-cores
inferredcites →https://doi.org/10.1145/2366231.2337164openalex-snapshot
Towards energy-proportional datacenter memory with mobile DRAM
inferredcites →https://doi.org/10.1145/2485922.2485957openalex-snapshot
Die-stacked DRAM caches for servers
inferredcites →https://doi.org/10.1145/279358.279387openalex-snapshot
Active pages: a computation model for intelligent memory
inferredcites →https://doi.org/10.1145/514191.514197openalex-snapshot
The architecture of the DIVA processing-in-memory chip
inferredcites →https://doi.org/10.2172/993908openalex-snapshot
Improving performance via mini-applications.
inferredcites →https://doi.org/10.5555/2499968.2499973openalex-snapshot
Exascale workload characterization and architecture implications

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.5281/zenodo.6942162openalex-extracted
inferred← citeshttps://doi.org/10.1007/978-3-030-20656-7_5openalex-snapshot
A Near-Data Processing Server Architecture and Its Impact on Data Center Applications
inferred← citeshttps://doi.org/10.1007/978-3-030-37277-4_20openalex-snapshot
Bitmap Index: A Processing-in-Memory Reconfigurable Implementation
inferred← citeshttps://doi.org/10.1007/978-3-031-01763-6openalex-snapshot
Innovations in the Memory System
inferred← citeshttps://doi.org/10.1007/978-3-031-02063-6_9openalex-snapshot
On the Reliability of Computing-in-Memory Accelerators for Deep Neural Networks
inferred← citeshttps://doi.org/10.1007/978-3-031-34214-1_5openalex-snapshot
Exploiting Heterogeneity in PIM Architectures for Data-Intensive Applications
inferred← citeshttps://doi.org/10.1007/978-3-031-42785-5_18openalex-snapshot
Optimization of OLAP In-Memory Database Management Systems with Processing-In-Memory Architecture
inferred← citeshttps://doi.org/10.1007/978-3-319-14313-2_36openalex-snapshot
Improving Node-Level MapReduce Performance Using Processing-in-Memory Technologies
inferred← citeshttps://doi.org/10.1007/978-3-319-16086-3_4openalex-snapshot
Processing-in-Memory: Exploring the Design Space
inferred← citeshttps://doi.org/10.1007/978-3-319-54313-0_10openalex-snapshot
Processing-In-Memory Architecture Design for Accelerating Neuro-Inspired Algorithms
inferred← citeshttps://doi.org/10.1007/978-3-319-54999-6_17openalex-snapshot
DVFS Space Exploration in Power Constrained Processing-in-Memory Systems
inferred← citeshttps://doi.org/10.1007/978-3-319-90385-9_5openalex-snapshot
The Processing-in-Memory Paradigm: Mechanisms to Enable Adoption
inferred← citeshttps://doi.org/10.1007/978-981-16-7487-7_7openalex-snapshot
A Modern Primer on Processing in Memory
inferred← citeshttps://doi.org/10.1007/978-981-19-0707-4_66openalex-snapshot
Near Data Processing and Its Applications
inferred← citeshttps://doi.org/10.1007/978-981-99-4764-5_18openalex-snapshot
An HBM3 Processing-In-Memory Architecture for Security and Data Integrity: Case Study
inferred← citeshttps://doi.org/10.1007/s10586-018-2844-1openalex-snapshot
A programmable shared-memory system for an array of processing-in-memory devices
inferred← citeshttps://doi.org/10.1007/s10766-020-00674-yopenalex-snapshot
Enabling Near-Data Accelerators Adoption by Through Investigation of Datapath Solutions
inferred← citeshttps://doi.org/10.1007/s11227-021-03661-3openalex-snapshot
Enabling fast and energy-efficient FM-index exact matching using processing-near-memory
inferred← citeshttps://doi.org/10.1007/s11265-025-01974-7openalex-snapshot
An Experimental Exploration of In-Memory Computing for Multi-Layer Perceptrons
inferred← citeshttps://doi.org/10.1007/s13222-023-00456-zopenalex-snapshot
Accelerating Large Table Scan Using Processing-In-Memory Technology
inferred← citeshttps://doi.org/10.1007/s41939-024-00517-0openalex-snapshot
In-memory computing: characteristics, spintronics, and neural network applications insights
inferred← citeshttps://doi.org/10.1007/s43207-025-00516-yopenalex-snapshot
Highly reliable ferroelectricity of HfO2–TiO2 nanolaminates thin films grown by plasma-enhanced atomic layer deposition
inferred← citeshttps://doi.org/10.1016/bs.adcom.2017.04.004openalex-snapshot
Simple Operations in Memory to Reduce Data Movement
inferred← citeshttps://doi.org/10.1016/j.memori.2023.100051openalex-snapshot
A review on computational storage devices and near memory computing for high performance applications
inferred← citeshttps://doi.org/10.1016/j.micpro.2017.01.005openalex-snapshot
Optimizing power efficiency for 3D stacked GPU-in-memory architecture
inferred← citeshttps://doi.org/10.1016/j.micpro.2019.01.009openalex-snapshot
Processing data where it makes sense: Enabling in-memory computation
inferred← citeshttps://doi.org/10.1016/j.micpro.2019.06.002openalex-snapshot
A Technologically Agnostic Framework for Cyber-Physical and IoT Processing-in-Memory-based Systems Simulation
inferred← citeshttps://doi.org/10.1016/j.micpro.2019.102868openalex-snapshot
Near-memory computing: Past, present, and future
inferred← citeshttps://doi.org/10.1016/j.parco.2023.103017openalex-snapshot
A heterogeneous processing-in-memory approach to accelerate quantum chemistry simulation
inferred← citeshttps://doi.org/10.1016/j.sysarc.2016.08.001openalex-snapshot
Exploring the Processing-in-Memory design space
inferred← citeshttps://doi.org/10.1016/j.sysarc.2021.102123openalex-snapshot
An efficient highly parallelized ReRAM-based architecture for motion estimation of HEVC
inferred← citeshttps://doi.org/10.1016/j.vlsi.2019.02.007openalex-snapshot
Exploiting the Logic-In-Memory paradigm for speeding-up data-intensive algorithms
inferred← citeshttps://doi.org/10.1021/acs.nanolett.5c02634openalex-snapshot
Multilevel Nanoarray Spin–Orbit Torque Device for Process-in-Memory Applications
inferred← citeshttps://doi.org/10.1049/iet-cdt.2020.0008openalex-snapshot
In memory computation using quantum‐dot cellular automata
inferred← citeshttps://doi.org/10.1109/access.2020.2983432openalex-snapshot
Making Better Use of Processing-in-Memory Through Potential-Based Task Offloading
inferred← citeshttps://doi.org/10.1109/access.2021.3110993openalex-snapshot
DAMOV: A New Methodology and Benchmark Suite for Evaluating Data Movement Bottlenecks
inferred← citeshttps://doi.org/10.1109/access.2022.3174101openalex-snapshot
Benchmarking a New Paradigm: Experimental Analysis and Characterization of a Real Processing-in-Memory System
inferred← citeshttps://doi.org/10.1109/access.2023.3252002openalex-snapshot
Casper: Accelerating Stencil Computations Using Near-Cache Processing
inferred← citeshttps://doi.org/10.1109/access.2024.3450105openalex-snapshot
Beyond Von Neumann Architectures: Exploring Algorithmic Opportunities via Octantis
inferred← citeshttps://doi.org/10.1109/aspdac.2017.7858355openalex-snapshot
ApproxPIM: Exploiting realistic 3D-stacked DRAM for energy-efficient processing in-memory
inferred← citeshttps://doi.org/10.1109/asscc.2018.8579261openalex-snapshot
Practical Challenges in Supporting Function in Memory
inferred← citeshttps://doi.org/10.1109/async.2018.00037openalex-snapshot
Case Study of Process Variation-Based Domain Partitioning of GPGPUs
inferred← citeshttps://doi.org/10.1109/ccgrid.2017.72openalex-snapshot
AnalyzeThat: A Programmable Shared-Memory System for an Array of Processing-In-Memory Devices
inferred← citeshttps://doi.org/10.1109/dsd.2018.00106openalex-snapshot
A Review of Near-Memory Computing Architectures: Opportunities and Challenges
inferred← citeshttps://doi.org/10.1109/dsd.2019.00093openalex-snapshot
Platform Independent Software Analysis for Near Memory Computing
inferred← citeshttps://doi.org/10.1109/dsd53832.2021.00048openalex-snapshot
NMPO: Near-Memory Computing Profiling and Offloading
inferred← citeshttps://doi.org/10.1109/dsn58291.2024.00024openalex-snapshot
Simultaneous Many-Row Activation in Off-the-Shelf DRAM Chips: Experimental Characterization and Analysis
inferred← citeshttps://doi.org/10.1109/fpl50879.2020.00014openalex-snapshot
NERO: A Near High-Bandwidth Memory Stencil Accelerator for Weather Prediction Modeling
inferred← citeshttps://doi.org/10.1109/hotchips.2014.7478840openalex-snapshot
Memory processing units
inferred← citeshttps://doi.org/10.1109/hpca.2015.7056040openalex-snapshot
NDA: Near-DRAM acceleration architecture leveraging commodity DRAM devices and standard memory modules
inferred← citeshttps://doi.org/10.1109/hpca.2015.7056063openalex-snapshot
GPGPU performance and power estimation using machine learning
inferred← citeshttps://doi.org/10.1109/hpca.2016.7446059openalex-snapshot
HRL: Efficient and flexible reconfigurable logic for near-data processing
inferred← citeshttps://doi.org/10.1109/hpca.2017.37openalex-snapshot
Processing-in-Memory Enabled Graphics Processors for 3D Rendering
inferred← citeshttps://doi.org/10.1109/hpca.2017.55openalex-snapshot
PipeLayer: A Pipelined ReRAM-Based Accelerator for Deep Learning
inferred← citeshttps://doi.org/10.1109/hpca.2018.00054openalex-snapshot
PM3: Power Modeling and Power Management for Processing-in-Memory
inferred← citeshttps://doi.org/10.1109/hpca.2019.00011openalex-snapshot
D-RaNGe: Using Commodity DRAM Devices to Generate True Random Numbers with Low Latency and High Throughput
inferred← citeshttps://doi.org/10.1109/hpca.2019.00013openalex-snapshot
PIM-VR: Erasing Motion Anomalies In Highly-Interactive Virtual Reality World with Customized Memory Cube
inferred← citeshttps://doi.org/10.1109/hpca47549.2020.00051openalex-snapshot
Enabling Highly Efficient Capsule Networks Processing Through A PIM-Based Architecture Design
inferred← citeshttps://doi.org/10.1109/hpca47549.2020.00052openalex-snapshot
Fulcrum: A Simplified Control and Access Mechanism Toward Flexible and Practical In-Situ Accelerators
inferred← citeshttps://doi.org/10.1109/hpca51647.2021.00030openalex-snapshot
GradPIM: A Practical Processing-in-DRAM Architecture for Gradient Descent
inferred← citeshttps://doi.org/10.1109/hpca51647.2021.00055openalex-snapshot
SpaceA: Sparse Matrix Vector Multiplication on Processing-in-Memory Accelerator
inferred← citeshttps://doi.org/10.1109/hpca53966.2022.00087openalex-snapshot
DR-STRaNGe: End-to-End System Design for DRAM-based True Random Number Generators
inferred← citeshttps://doi.org/10.1109/hpca56546.2023.10071005openalex-snapshot
DIMM-Link: Enabling Efficient Inter-DIMM Communication for Near-Memory Processing
inferred← citeshttps://doi.org/10.1109/hpca57654.2024.00021openalex-snapshot
Bandwidth-Effective DRAM Cache for GPU s with Storage-Class Memory
inferred← citeshttps://doi.org/10.1109/hpca57654.2024.00024openalex-snapshot
MIMDRAM: An End-to-End Processing-Using-DRAM System for High-Throughput, Energy-Efficient and Programmer-Transparent Multiple-Instruction Multiple-Data Computing
inferred← citeshttps://doi.org/10.1109/hpca57654.2024.00034openalex-snapshot
Smart-Infinity: Fast Large Language Model Training using Near-Storage Processing on a Real System
inferred← citeshttps://doi.org/10.1109/hpcc/smartcity/dss.2018.00119openalex-snapshot
3D-DRAM Performance for Different OpenMP Scheduling Techniques in Multicore Systems
inferred← citeshttps://doi.org/10.1109/hpec.2018.8547571openalex-snapshot
Designing Algorithms for the EMU Migrating-threads-based Architecture
inferred← citeshttps://doi.org/10.1109/ia3.2016.007openalex-snapshot
Highly Scalable Near Memory Processing with Migrating Threads on the Emu System Architecture
inferred← citeshttps://doi.org/10.1109/iccad57390.2023.10323699openalex-snapshot
Runtime Row/Column Activation Pruning for ReRAM-based Processing-in-Memory DNN Accelerators
inferred← citeshttps://doi.org/10.1109/iccad66269.2025.11240646openalex-snapshot
GenomeDPU: A Cost-Effective In-Memory Data Processing Unit for GPU-based Genome Analysis
inferred← citeshttps://doi.org/10.1109/iccd.2016.7753257openalex-snapshot
Accelerating pointer chasing in 3D-stacked memory: Challenges, mechanisms, evaluation
inferred← citeshttps://doi.org/10.1109/iccd50377.2020.00035openalex-snapshot
NATSA: A Near-Data Processing Accelerator for Time Series Analysis
inferred← citeshttps://doi.org/10.1109/icce-taiwan49838.2020.9258069openalex-snapshot
Reconfigurable MAC Systolic Array Architecture Design for Three-Dimensional Convolution Neural Network
inferred← citeshttps://doi.org/10.1109/icdcs.2018.00130openalex-snapshot
Computing In-Memory, Revisited
inferred← citeshttps://doi.org/10.1109/icde53745.2022.00270openalex-snapshot
Polynesia: Enabling High-Performance and Energy-Efficient Hybrid Transactional/Analytical Databases with Hardware/Software Co-Design
inferred← citeshttps://doi.org/10.1109/icdew58674.2023.00035openalex-snapshot
Adaptive Query Compilation with Processing-in-Memory
inferred← citeshttps://doi.org/10.1109/iceeps62542.2024.10693073openalex-snapshot
Application and Challenges of In-Memory Computing in Power System Simulation
inferred← citeshttps://doi.org/10.1109/icmlca66850.2025.11336794openalex-snapshot
PIM-AD: A PIM Architecture for CNN-Based Anomaly Detection
inferred← citeshttps://doi.org/10.1109/icppw.2016.31openalex-snapshot
Performance Implications of Processing-in-Memory Designs on Data-Intensive Applications
inferred← citeshttps://doi.org/10.1109/igsc54211.2021.9651614openalex-snapshot
Benchmarking Memory-Centric Computing Systems: Analysis of Real Processing-In-Memory Hardware
inferred← citeshttps://doi.org/10.1109/iiswc.2017.8167757openalex-snapshot
Demystifying the characteristics of 3D-stacked memories: A case study for Hybrid Memory Cube
inferred← citeshttps://doi.org/10.1109/ipdps.2017.12openalex-snapshot
Similarity Search on Automata Processors
inferred← citeshttps://doi.org/10.1109/ipdps.2018.00099openalex-snapshot
Application Codesign of Near-Data Processing for Similarity Search
inferred← citeshttps://doi.org/10.1109/ipdpsw.2016.205openalex-snapshot
Fine-Grained Task Migration for Graph Algorithms Using Processing in Memory
inferred← citeshttps://doi.org/10.1109/isca.2016.13openalex-snapshot
PRIME: A Novel Processing-in-Memory Architecture for Neural Network Computation in ReRAM-Based Main Memory
inferred← citeshttps://doi.org/10.1109/isca.2016.27openalex-snapshot
Transparent Offloading and Mapping (TOM): Enabling Programmer-Transparent Near-Data Processing in GPU Systems
inferred← citeshttps://doi.org/10.1109/isca.2016.46openalex-snapshot
Accelerating Dependent Cache Misses with an Enhanced Memory Controller
inferred← citeshttps://doi.org/10.1109/isca45697.2020.00058openalex-snapshot
TVARAK: Software-Managed Hardware Offload for Redundancy in Direct-Access NVM Storage
inferred← citeshttps://doi.org/10.1109/isca45697.2020.00072openalex-snapshot
Near Data Acceleration with Concurrent Host Access
inferred← citeshttps://doi.org/10.1109/isca45697.2020.00074openalex-snapshot
Hyper-Ap: Enhancing Associative Processing Through A Full-Stack Optimization
inferred← citeshttps://doi.org/10.1109/isca52012.2021.00027openalex-snapshot
ABC-DIMM: Alleviating the Bottleneck of Communication in DIMM-based Near-Memory Processing with Inter-DIMM Broadcast
inferred← citeshttps://doi.org/10.1109/isca52012.2021.00078openalex-snapshot
QUAC-TRNG: High-Throughput True Random Number Generation Using Quadruple Row Activation in Commodity DRAM Chips
inferred← citeshttps://doi.org/10.1109/isca59077.2024.00052openalex-snapshot
NDPBridge: Enabling Cross-Bank Coordination in Near-DRAM-Bank Processing Architectures
inferred← citeshttps://doi.org/10.1109/iscas.2019.8702339openalex-snapshot
Exploration of a PIM Design Configuration for Energy-Efficient Task Offloading
inferred← citeshttps://doi.org/10.1109/iscas.2019.8702534openalex-snapshot
Programmable Non-Volatile Memory Design Featuring Reconfigurable In-Memory Operations
inferred← citeshttps://doi.org/10.1109/iscas45731.2020.9181068openalex-snapshot
Towards a Reconfigurable Bit-Serial/Bit-Parallel Vector Accelerator using In-Situ Processing-In-SRAM
inferred← citeshttps://doi.org/10.1109/iscas48785.2022.9937586openalex-snapshot
An Automated Approach to Compare Bit Serial and Bit Parallel In-Memory Computing for DNNs
inferred← citeshttps://doi.org/10.1109/iscas51556.2021.9401315openalex-snapshot
Transport Triggered near Memory Accelerator for Deep Learning
inferred← citeshttps://doi.org/10.1109/ispa/iucc.2017.00061openalex-snapshot
An Efficient Racetrack Memory-Based Processing-in-Memory Architecture for Convolutional Neural Networks
inferred← citeshttps://doi.org/10.1109/ispass.2018.00018openalex-snapshot
Performance Implications of NoCs on 3D-Stacked Memories: Insights from the Hybrid Memory Cube
inferred← citeshttps://doi.org/10.1109/ispass57527.2023.00013openalex-snapshot
Evaluating Machine LearningWorkloads on Memory-Centric Computing Systems
inferred← citeshttps://doi.org/10.1109/ispass57527.2023.00031openalex-snapshot
TransPimLib: Efficient Transcendental Functions for Processing-in-Memory Systems
inferred← citeshttps://doi.org/10.1109/isvlsi54635.2022.00064openalex-snapshot
Machine Learning Training on a Real Processing-in-Memory System
inferred← citeshttps://doi.org/10.1109/jetcas.2022.3167391openalex-snapshot
ADC-PIM: Accelerating Convolution on the GPU via In-Memory Approximate Data Comparison
inferred← citeshttps://doi.org/10.1109/jproc.2015.2435018openalex-snapshot
Evolution of Memory Architecture
inferred← citeshttps://doi.org/10.1109/lca.2015.2434872openalex-snapshot
Fast Bulk Bitwise AND and OR in DRAM
inferred← citeshttps://doi.org/10.1109/lca.2016.2577557openalex-snapshot
LazyPIM: An Efficient Cache Coherence Mechanism for Processing-in-Memory
inferred← citeshttps://doi.org/10.1109/lca.2019.2894800openalex-snapshot
A Case For Asymmetric Processing in Memory
inferred← citeshttps://doi.org/10.1109/lca.2022.3208255openalex-snapshot
Pulley: An Algorithm/Hardware Co-Optimization for In-Memory Sorting
inferred← citeshttps://doi.org/10.1109/mcas.2021.3092533openalex-snapshot
Compute-in-Memory Chips for Deep Learning: Recent Trends and Prospects
inferred← citeshttps://doi.org/10.1109/mdat.2017.2779742openalex-snapshot
Emerging Accelerator Platforms for Data Centers
inferred← citeshttps://doi.org/10.1109/mdat.2021.3095225openalex-snapshot
A Case for PIM Support in General-Purpose Compilers
inferred← citeshttps://doi.org/10.1109/micro.2016.7783753openalex-snapshot
Chameleon: Versatile and practical near-DRAM acceleration architecture for large memory systems
inferred← citeshttps://doi.org/10.1109/micro.2018.00058openalex-snapshot
Adaptive Scheduling for Systems with Asymmetric Memory Hierarchies
inferred← citeshttps://doi.org/10.1109/micro.2018.00059openalex-snapshot
Processing-in-Memory for Energy-Efficient Neural Network Training: A Heterogeneous Approach
inferred← citeshttps://doi.org/10.1109/micro.2018.00070openalex-snapshot
Application-Transparent Near-Memory Processing Architecture with Memory Channel Network
inferred← citeshttps://doi.org/10.1109/micro50266.2020.00039openalex-snapshot
DUAL: Acceleration of Clustering Algorithms using Digital-based Processing In-Memory
inferred← citeshttps://doi.org/10.1109/micro56248.2022.00059openalex-snapshot
Sparse Attention Acceleration with Synergistic In-Memory Pruning and On-Chip Recomputation
inferred← citeshttps://doi.org/10.1109/micro56248.2022.00067openalex-snapshot
pLUTo: Enabling Massively Parallel Computation in DRAM via Lookup Tables
inferred← citeshttps://doi.org/10.1109/micro56248.2022.00069openalex-snapshot
Flash-Cosmos: In-Flash Bulk Bitwise Operations Using Inherent Computation Capability of NAND Flash Memory
inferred← citeshttps://doi.org/10.1109/micro61859.2024.00051openalex-snapshot
Low-Overhead General-Purpose Near-Data Processing in CXL Memory Expanders
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Leviathan: A Unified System for General-Purpose Near-Data Computing
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PointCIM: A Computing-in-Memory Architecture for Accelerating Deep Point Cloud Analytics
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Duplex: A Device for Large Language Models with Mixture of Experts, Grouped Query Attention, and Continuous Batching
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Achieving Exascale Capabilities through Heterogeneous Computing
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Near-DRAM Acceleration with Single-ISA Heterogeneous Processing in Standard Memory Modules
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Near-Memory Data Services
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Blurring the Lines between Memory and Computation
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Reflections on Progress in Digital Circuits: From basics to untangle past trials
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Practical Near-Data Processing for In-Memory Analytics Frameworks
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BSSync: Processing Near Memory for Machine Learning Workloads with Bounded Staleness Consistency Models
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POSTER: DaPPA: A Data-Parallel Programming Framework for Processing-in-Memory Architectures
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3D-PIM NoCs with Multiple Subnetworks: A Performance and Power Evaluation
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The Non-Uniform Compute Device (NUCD) Architecture for Lightweight Accelerator Offload
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Off-Chip Congestion Management for GPU-based Non-Uniform Processing-in-Memory Networks
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A generic processing in memory cycle accurate simulator under hybrid memory cube architecture
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Progressive Codesign of an Architecture and Compiler Using a Proxy Application
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Efficient Online 4D Magnetic Resonance Imaging
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A Multi-Domain Architectural Efficiency Metric
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In-Memory Processing on the Spintronic CRAM: From Hardware Design to Application Mapping
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RC-NVM: Dual-Addressing Non-Volatile Memory Architecture Supporting Both Row and Column Memory Accesses
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BLADE: An in-Cache Computing Architecture for Edge Devices
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A Lightweight and Efficient GPU for NDP Utilizing Data Access Pattern of Image Processing
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Enabling Highly Efficient Capsule Networks Processing Through Software-Hardware Co-Design
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Accelerating Graph Convolutional Networks Through a PIM-Accelerated Approach
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TSV-Based 3-D ICs: Design Methods and Tools
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RowHammer: A Retrospective
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Eva-CiM: A System-Level Performance and Energy Evaluation Framework for Computing-in-Memory Architectures
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A Practical Highly Paralleled ReRAM-Based DNN Accelerator by Reusing Weight Pattern Repetitions
inferred← citeshttps://doi.org/10.1109/tcpmt.2021.3117071openalex-snapshot
Signal Integrity and Computing Performance Analysis of a Processing-In-Memory of High Bandwidth Memory (PIM-HBM) Scheme
inferred← citeshttps://doi.org/10.1109/tetc.2021.3115495openalex-snapshot
Near Volatile and Non-Volatile Memory Processing in 3D Systems
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Efficient Spectral Graph Convolutional Network Deployment on Memristive Crossbars
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IMCS2: Novel Device-to-Architecture Co-Design for Low-Power In-Memory Computing Platform Using Coterminous Spin Switch
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Designing Efficient Bit-Level Sparsity-Tolerant Memristive Networks
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AutoGMap: Learning to Map Large-Scale Sparse Graphs on Memristive Crossbars
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Hardware Accelerator Integration Tradeoffs for High-Performance Computing: A Case Study of GEMM Acceleration in N-Body Methods
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GIRAF: General Purpose In-Storage Resistive Associative Framework
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Logic-Base Interconnect Design for Near Memory Computing in the Smart Memory Cube
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Excavating the Hidden Parallelism Inside DRAM Architectures With Buffered Compares
inferred← citeshttps://doi.org/10.1109/tvlsi.2017.2776954openalex-snapshot
Computing in Memory With Spin-Transfer Torque Magnetic RAM
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Sparse Vector-Matrix Multiplication Acceleration in Diode-Selected Crossbars
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TensorCache: Reconstructing Memory Architecture With SRAM-Based In-Cache Computing for Efficient Tensor Computations in GPGPUs
inferred← citeshttps://doi.org/10.1145/2686875openalex-snapshot
GP-SIMD Processing-in-Memory
inferred← citeshttps://doi.org/10.1145/2742854.2742863openalex-snapshot
Data access optimization in a processing-in-memory system
inferred← citeshttps://doi.org/10.1145/2749469.2750385openalex-snapshot
PIM-enabled instructions
inferred← citeshttps://doi.org/10.1145/2749469.2750386openalex-snapshot
A scalable processing-in-memory accelerator for parallel graph processing
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Data reorganization in memory using 3D-stacked DRAM
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Beyond the Wall
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Near Data Processing
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Understanding Energy Aspects of Processing-near-Memory for HPC Workloads
inferred← citeshttps://doi.org/10.1145/2830772.2830788openalex-snapshot
Enabling portable energy efficiency with memory accelerated library
inferred← citeshttps://doi.org/10.1145/2872887.2750385openalex-snapshot
PIM-enabled instructions
inferred← citeshttps://doi.org/10.1145/2872887.2750386openalex-snapshot
A scalable processing-in-memory accelerator for parallel graph processing
inferred← citeshttps://doi.org/10.1145/2872887.2750397openalex-snapshot
Data reorganization in memory using 3D-stacked DRAM
inferred← citeshttps://doi.org/10.1145/2925426.2926282openalex-snapshot
Prefetching Techniques for Near-memory Throughput Processors
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Scheduling Techniques for GPU Architectures with Processing-In-Memory Capabilities
inferred← citeshttps://doi.org/10.1145/2989081.2989087openalex-snapshot
Data-Centric Computing Frontiers
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Integrated Thermal Analysis for Processing In Die-Stacking Memory
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AIM
inferred← citeshttps://doi.org/10.1145/3007787.3001140openalex-snapshot
PRIME
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Transparent offloading and mapping (TOM)
inferred← citeshttps://doi.org/10.1145/3007787.3001184openalex-snapshot
Accelerating dependent cache misses with an enhanced memory controller
inferred← citeshttps://doi.org/10.1145/3075564.3075584openalex-snapshot
Selective off-loading to Memory
inferred← citeshttps://doi.org/10.1145/3087556.3087582openalex-snapshot
Concurrent Data Structures for Near-Memory Computing
inferred← citeshttps://doi.org/10.1145/3120895.3120900openalex-snapshot
Dataflow based Near Data Computing Achieves Excellent Energy Efficiency
inferred← citeshttps://doi.org/10.1145/3123939.3123977openalex-snapshot
DRISA
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Ambit
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Toward standardized near-data processing with unrestricted data placement for GPUs
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An Architecture for Integrated Near-Data Processors
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Lightweight SIMT core designs for intelligent 3D stacked DRAM
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PHOENIX
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Performance Evaluation of Mesh-based 3D NoCs
inferred← citeshttps://doi.org/10.1145/3155287openalex-snapshot
CAIRO
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Triple Engine Processor (TEP)
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In-Memory Data Parallel Processor
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Google Workloads for Consumer Devices
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A Novel ReRAM-Based Processing-in-Memory Architecture for Graph Traversal
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Towards Near-Data Processing of Compare Operations in 3D-Stacked Memory
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Design space exploration for PIM architectures in 3D-stacked memories
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