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Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/978-0-387-09766-4_133openalex-snapshot
NAS Parallel Benchmarks
inferredcites →https://doi.org/10.1007/978-3-642-32627-1_11openalex-snapshot
Time and Cost-Efficient Modeling and Generation of Large-Scale TPCC/TPCE/TPCH Workloads
inferredcites →https://doi.org/10.1109/date.2004.1268792openalex-snapshot
Proceedings Design, Automation and Test in Europe Conference and Exhibition
inferredcites →https://doi.org/10.1109/dcc.2006.22openalex-snapshot
Data Compression with Restricted Parsings
inferredcites →https://doi.org/10.1109/icde.2006.150openalex-snapshot
Super-Scalar RAM-CPU Cache Compression
inferredcites →https://doi.org/10.1109/isca.2005.6openalex-snapshot
A robust main-memory compression scheme
inferredcites →https://doi.org/10.1109/isca.2008.7openalex-snapshot
Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems
inferredcites →https://doi.org/10.1109/ispass.2013.6557148openalex-snapshot
McSimA+: A manycore simulator with application-level+ simulation and detailed microarchitecture modeling
inferredcites →https://doi.org/10.1109/micro.2004.22openalex-snapshot
Memory Controller Optimizations for Web Servers
inferredcites →https://doi.org/10.1145/1080695.1069978openalex-snapshot
A Robust Main-Memory Compression Scheme
inferredcites →https://doi.org/10.1145/1394608.1382128openalex-snapshot
Parallelism-Aware Batch Scheduling
inferredcites →https://doi.org/10.1145/144965.145003openalex-snapshot
Executing compressed programs on an embedded RISC architecture
inferredcites →https://doi.org/10.1145/1555754.1555760openalex-snapshot
Scalable high performance main memory system using phase-change memory technology
inferredcites →https://doi.org/10.1145/1555754.1555789openalex-snapshot
Disaggregated memory for expansion and sharing in blade servers
inferredcites →https://doi.org/10.1145/2000064.2000108openalex-snapshot
Dark silicon and the end of multicore scaling
inferredcites →https://doi.org/10.1145/2370816.2370870openalex-snapshot
Base-delta-immediate compression
inferredcites →https://doi.org/10.1145/2485922.2485926openalex-snapshot
Thin servers with smart pipes
inferredcites →https://doi.org/10.1145/2485922.2485943openalex-snapshot
Efficient virtual memory for big memory servers
inferredcites →https://doi.org/10.1145/264107.264207openalex-snapshot
Prefetching using Markov predictors
inferredcites →https://doi.org/10.1145/277044.277185openalex-snapshot
Code compression for embedded systems
inferredcites →https://doi.org/10.1145/356989.357003openalex-snapshot
Frequent value locality and value-centric data cache design
inferredcites →https://doi.org/10.1145/360128.360154openalex-snapshot
Frequent value compression in data caches
inferredcites →https://doi.org/10.1145/378993.379235openalex-snapshot
Frequent value locality and value-centric data cache design
inferredcites →https://doi.org/10.1147/rd.452.0271openalex-snapshot
IBM Memory Expansion Technology (MXT)
inferredcites →https://doi.org/10.5555/968880.969268openalex-snapshot
LZW-based code compression for VLIW embedded systems
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1002/cpe.8290openalex-snapshot
A low‐latency memory‐cube network with dual diagonal mesh topology and bypassed pipelines
inferred← citeshttps://doi.org/10.1016/b978-0-32-390796-5.00011-5openalex-snapshot
Storage technologies and their data
inferred← citeshttps://doi.org/10.1109/candar60563.2023.00013openalex-snapshot
Dual Diagonal Mesh: An Optimal Memory Cube Network Under Geometric Constraints
inferred← citeshttps://doi.org/10.1109/hpca.2016.7446064openalex-snapshot
A case for toggle-aware compression for GPU systems
inferred← citeshttps://doi.org/10.1109/hpca.2019.00016openalex-snapshot
String Figure: A Scalable and Elastic Memory Network Architecture
inferred← citeshttps://doi.org/10.1109/hpca53966.2022.00084openalex-snapshot
Exploiting Inter-block Entropy to Enhance the Compressibility of Blocks with Diverse Data
inferred← citeshttps://doi.org/10.1109/icde65448.2025.00037openalex-snapshot
A Cost-Effective and Decompression-Transparent Compressor for OLTP-Oriented Databases
inferred← citeshttps://doi.org/10.1109/ipdps.2019.00091openalex-snapshot
Drowsy-DC: Data Center Power Management System
inferred← citeshttps://doi.org/10.1109/ipdps65963.2026.00045openalex-snapshot
COMPAT: A Compression Framework with Fine-Grain and Object-Level Compression Units
inferred← citeshttps://doi.org/10.1109/isca45697.2020.00080openalex-snapshot
Buddy Compression: Enabling Larger Memory for Deep Learning and HPC Workloads on GPUs
inferred← citeshttps://doi.org/10.1109/isca52012.2021.00030openalex-snapshot
BOSS: Bandwidth-Optimized Search Accelerator for Storage-Class Memory
inferred← citeshttps://doi.org/10.1109/isca59077.2024.00085openalex-snapshot
DyLeCT: Achieving Huge-page-like Translation Performance for Hardware-compressed Memory
inferred← citeshttps://doi.org/10.1109/isca66397.2026.00107openalex-snapshot
Random-Access Hardware Sequence Compression
inferred← citeshttps://doi.org/10.1109/lca.2018.2821163openalex-snapshot
CompressPoints: An Evaluation Methodology for Compressed Memory Systems
inferred← citeshttps://doi.org/10.1109/micro.2016.7783732openalex-snapshot
A unified memory network architecture for in-memory computing in commodity servers
inferred← citeshttps://doi.org/10.1109/micro.2018.00051openalex-snapshot
Compresso: Pragmatic Main Memory Compression
inferred← citeshttps://doi.org/10.1109/micro61859.2024.00075openalex-snapshot
Memory Allocation Under Hardware Compression
inferred← citeshttps://doi.org/10.1109/pact.2017.12openalex-snapshot
Transparent Dual Memory Compression Architecture
inferred← citeshttps://doi.org/10.1109/tc.2026.3666458openalex-snapshot
TRACE: Unlocking Effective CXL Bandwidth via Lossless Compression and Precision Scaling
inferred← citeshttps://doi.org/10.1145/3591195.3595273openalex-snapshot
ZipKV: In-Memory Key-Value Store with Built-In Data Compression
inferred← citeshttps://doi.org/10.1145/3673038.3673058openalex-snapshot
Selective Memory Compression for GPU Memory Oversubscription Management
inferred← citeshttps://doi.org/10.1145/3695794.3695805openalex-snapshot
ZipCache: A DRAM/SSD Cache with Built-in Transparent Compression
inferred← citeshttps://doi.org/10.1145/3779212.3790250openalex-snapshot
Z ip S erv : Fast and Memory-Efficient LLM Inference with Hardware-Aware Lossless Compression
inferred← citeshttps://doi.org/10.1145/3789240.3829204openalex-snapshot
ZipCCL: Efficient Lossless Data Compression of Communication Collectives for Accelerating LLM Training
inferred← citeshttps://doi.org/10.14778/3648160.3648166openalex-snapshot
Accelerating Sampling and Aggregation Operations in GNN Frameworks with GPU Initiated Direct Storage Accesses
inferred← citeshttps://doi.org/10.3390/app131810526openalex-snapshot
QZRAM: A Transparent Kernel Memory Compression System Design for Memory-Intensive Applications with QAT Accelerator Integration
inferred← citeshttps://doi.org/10.48550/arxiv.1609.02067openalex-snapshot
Practical Data Compression for Modern Memory Hierarchies
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