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Memory Controller Optimizations for Web Servers
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1109/12.895941openalex-snapshot
Dynamic access ordering for streamed computations
inferredcites →https://doi.org/10.1109/2.982916openalex-snapshot
Simics: A full system simulation platform
inferredcites →https://doi.org/10.1109/hpca.1999.744334openalex-snapshot
Impulse: building a smarter memory controller
inferredcites →https://doi.org/10.1109/hpca.2000.824337openalex-snapshot
Design of a parallel vector access unit for SDRAM memory systems
inferredcites →https://doi.org/10.1109/hpca.2001.903272openalex-snapshot
Reducing DRAM latencies with an integrated memory hierarchy design
inferredcites →https://doi.org/10.1109/isca.1999.765953openalex-snapshot
A performance comparison of contemporary DRAM architectures
inferredcites →https://doi.org/10.1109/pact.1998.727154openalex-snapshot
Command vector memory systems: high performance at low cost
inferredcites →https://doi.org/10.1145/300979.300998openalex-snapshot
A performance comparison of contemporary DRAM architectures
inferredcites →https://doi.org/10.1145/360128.360132openalex-snapshot
Eager writeback - a technique for improving bandwidth utilization
inferredcites →https://doi.org/10.1145/360128.360134openalex-snapshot
A permutation-based page interleaving scheme to reduce row-buffer conflicts and exploit data locality
inferredcites →https://doi.org/10.1145/379240.379252openalex-snapshot
Concurrency, latency, or system overhead
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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Memory Access Pattern-Aware DRAM Controller Design for Mixed-Criticality Systems
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A Fair Thread-Aware Memory Scheduling Algorithm for Chip Multiprocessor
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Optimizing memory access traffic via runtime thread migration for on-chip distributed memory systems
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PARBLO: Page-Allocation-Based DRAM Row Buffer Locality Optimization
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Direct distributed memory access for CMPs
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Memory access schedule minimization for embedded systems
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DAMOV: A New Methodology and Benchmark Suite for Evaluating Data Movement Bottlenecks
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GEMI: A High Performance and High Flexibility Memory Interface Architecture for Complex Embedded SOC
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Single-ended Coding Techniques for Off-chip Interconnects to Commodity Memory
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Exploiting Latency and Error Tolerance of GPGPU Applications for an Energy-Efficient DRAM
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Fully-Buffered DIMM Memory Architectures: Understanding Mechanisms, Overheads and Scaling
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A Burst Scheduling Access Reordering Mechanism
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ATLAS: A scalable and high-performance scheduling algorithm for multiple memory controllers
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Staged Reads: Mitigating the impact of DRAM writes on DRAM reads
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NUAT: A non-uniform access time memory controller
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Architecting an Energy-Efficient DRAM System for GPUs
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Cooperative Path-ORAM for Effective Memory Bandwidth Sharing in Server Settings
inferred← citeshttps://doi.org/10.1109/hpca.2018.00026openalex-snapshot
The DRAM Latency PUF: Quickly Evaluating Physical Unclonable Functions by Exploiting the Latency-Reliability Tradeoff in Modern Commodity DRAM Devices
inferred← citeshttps://doi.org/10.1109/hpca68181.2026.11408437openalex-snapshot
Conduit: Programmer-Transparent Near-Data Processing Using Multiple Compute-Capable Resources in Solid State Drives
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SmartMig: A Case for Page Migration and Self-Interleaving for On-Chip Distributed Memory Systems
inferred← citeshttps://doi.org/10.1109/iccd46524.2019.00022openalex-snapshot
Bandwidth-Aware Last-Level Caching: Efficiently Coordinating Off-Chip Read and Write Bandwidth
inferred← citeshttps://doi.org/10.1109/iceca.2018.8474846openalex-snapshot
Improving the Performance of Chip Multiprocessor by Delayed Write Drain and Prefetcher based Memory Scheduler
inferred← citeshttps://doi.org/10.1109/icpads.2009.86openalex-snapshot
Minimizing Memory Access Schedule for Memories
inferred← citeshttps://doi.org/10.1109/icpp.2008.53openalex-snapshot
Memory Access Scheduling Schemes for Systems with Multi-Core Processors
inferred← citeshttps://doi.org/10.1109/icsamos.2008.4664865openalex-snapshot
A priority-expression-based burst scheduling of memory reordering access
inferred← citeshttps://doi.org/10.1109/icsamos.2010.5642060openalex-snapshot
Interleaving granularity on high bandwidth memory architecture for CMPs
inferred← citeshttps://doi.org/10.1109/iiswc.2016.7581279openalex-snapshot
Memory controller design under cloud workloads
inferred← citeshttps://doi.org/10.1109/ipdps.2010.5470451openalex-snapshot
Fine-grained QoS scheduling for PCM-based main memory systems
inferred← citeshttps://doi.org/10.1109/ipdps.2013.85openalex-snapshot
An Analytical Performance Model for Partitioning Off-Chip Memory Bandwidth
inferred← citeshttps://doi.org/10.1109/ipdpsw.2015.30openalex-snapshot
Decoupling Contention with Victim Row-Buffer on Multicore Memory Systems
inferred← citeshttps://doi.org/10.1109/isca.2008.21openalex-snapshot
Self-Optimizing Memory Controllers: A Reinforcement Learning Approach
inferred← citeshttps://doi.org/10.1109/isca.2008.7openalex-snapshot
Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems
inferred← citeshttps://doi.org/10.1109/isca.2012.6237027openalex-snapshot
Improving writeback efficiency with decoupled last-write prediction
inferred← citeshttps://doi.org/10.1109/isca52012.2021.00019openalex-snapshot
PF-DRAM: A Precharge-Free DRAM Structure
inferred← citeshttps://doi.org/10.1109/ispa-bdcloud-sustaincom-socialcom48970.2019.00020openalex-snapshot
Self-Adaptive Address Mapping Mechanism for Access Pattern Awareness on DRAM
inferred← citeshttps://doi.org/10.1109/ispdc.2014.9openalex-snapshot
Agent-Based Memory Access for Many-Core CMPs
inferred← citeshttps://doi.org/10.1109/l-ca.2011.32openalex-snapshot
DRAM Scheduling Policy for GPGPU Architectures Based on a Potential Function
inferred← citeshttps://doi.org/10.1109/l-ca.2011.4openalex-snapshot
DRAMSim2: A Cycle Accurate Memory System Simulator
inferred← citeshttps://doi.org/10.1109/mcsoc.2014.50openalex-snapshot
Time-Based Least Memory Intensive Scheduling
inferred← citeshttps://doi.org/10.1109/mcsoc.2015.13openalex-snapshot
Adaptive Time-Based Least Memory Intensive Scheduling
inferred← citeshttps://doi.org/10.1109/micro.2007.21openalex-snapshot
Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors
inferred← citeshttps://doi.org/10.1109/micro.2007.40openalex-snapshot
Process Variation Tolerant 3T1D-Based Cache Architectures
inferred← citeshttps://doi.org/10.1109/micro.2008.4771791openalex-snapshot
Prefetch-Aware DRAM Controllers
inferred← citeshttps://doi.org/10.1109/micro.2012.35openalex-snapshot
Addressing End-to-End Memory Access Latency in NoC-Based Multicores
inferred← citeshttps://doi.org/10.1109/micro.2014.34openalex-snapshot
Compiler Support for Optimizing Memory Bank-Level Parallelism
inferred← citeshttps://doi.org/10.1109/micro.2014.47openalex-snapshot
FIRM: Fair and High-Performance Memory Control for Persistent Memory Systems
inferred← citeshttps://doi.org/10.1109/micro.2016.7783760openalex-snapshot
Improving bank-level parallelism for irregular applications
inferred← citeshttps://doi.org/10.1109/micro50266.2020.00036openalex-snapshot
FIGARO: Improving System Performance via Fine-Grained In-DRAM Data Relocation and Caching
inferred← citeshttps://doi.org/10.1109/mm.2009.12openalex-snapshot
Parallelism-Aware Batch Scheduling: Enabling High-Performance and Fair Shared Memory Controllers
inferred← citeshttps://doi.org/10.1109/mm.2009.77openalex-snapshot
Dynamic Multicore Resource Management: A Machine Learning Approach
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Effective Management of DRAM Bandwidth in Multicore Processors
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Combine thread with memory scheduling for maximizing performance in multi-core systems
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High-Performance Buffer Mapping to Exploit DRAM Concurrency in Multiprocessor DSP Systems
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Time-predictable DRAM access scheduling algorithms for real-time multicore processors
inferred← citeshttps://doi.org/10.1109/tc.2010.214openalex-snapshot
Prefetch-Aware Memory Controllers
inferred← citeshttps://doi.org/10.1109/tc.2013.76openalex-snapshot
Throughput Enhancement for Phase Change Memories
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RC-NVM: Dual-Addressing Non-Volatile Memory Architecture Supporting Both Row and Column Memory Accesses
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AttentionRC: A Novel Approach to Improve Locality Sensitive Hashing Attention on Dual-Addressing Memory
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Dynamic Transaction Management for System Level Quality-of-Service in Mobile APs
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High-Bandwidth Network Memory System Through Virtual Pipelines
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Integrated Memory Controllers with Parallel Coherence Streams
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Real-Time Scheduling for Phase Change Main Memory Systems
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A Study of Leveraging Memory Level Parallelism for DRAM System on Multi-core/Many-Core Architecture
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An Approach for Adaptive DRAM Temperature and Power Management
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Pragmatic Integration of an SRAM Row Cache in Heterogeneous 3-D DRAM Architecture Using TSV
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Interference-aware Batch Memory Scheduling in heterogeneous multicore architecture
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Intelligent Architectures for Intelligent Machines
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The bit-reversal SDRAM address mapping
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TCP offload through connection handoff
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TCP offload through connection handoff
inferred← citeshttps://doi.org/10.1145/1250662.1250701openalex-snapshot
Thermal modeling and management of DRAM memory systems
inferred← citeshttps://doi.org/10.1145/1314299.1314301openalex-snapshot
Memory scheduling for modern microprocessors
inferred← citeshttps://doi.org/10.1145/1363686.1364035openalex-snapshot
Exploiting program cyclic behavior to reduce memory latency in embedded processors
inferred← citeshttps://doi.org/10.1145/1375527.1375540openalex-snapshot
An approach for adaptive DRAM temperature and power management
inferred← citeshttps://doi.org/10.1145/1394608.1382128openalex-snapshot
Parallelism-Aware Batch Scheduling
inferred← citeshttps://doi.org/10.1145/1394608.1382172openalex-snapshot
Self-Optimizing Memory Controllers
inferred← citeshttps://doi.org/10.1145/2304576.2304613openalex-snapshot
Multiple sub-row buffers in DRAM
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Improving writeback efficiency with decoupled last-write prediction
inferred← citeshttps://doi.org/10.1145/2435227.2435260openalex-snapshot
Timing effects of DDR memory systems in hard real-time multicore architectures
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High-performance and low-energy buffer mapping method for multiprocessor DSP systems
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Regularities considered harmful
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Navigating big data with high-throughput, energy-efficient data partitioning
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Regularities considered harmful
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Regularities considered harmful
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Navigating big data with high-throughput, energy-efficient data partitioning
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Effect of page frame allocation pattern on bank conflicts in multi-core systems
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Reducing DRAM row activations with eager read/write clustering
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Application-aware Memory System for Fair and Efficient Execution of Concurrent GPGPU Applications
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Application-aware Memory System for Fair and Efficient Execution of Concurrent GPGPU Applications
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Energy Analysis of Hardware and Software Range Partitioning
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Memory Row Reuse Distance and its Role in Optimizing Application Performance
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Memory Row Reuse Distance and its Role in Optimizing Application Performance
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Anatomy of GPU Memory System for Multi-Application Execution
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Exploiting Core Criticality for Enhanced GPU Performance
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Exploiting Core Criticality for Enhanced GPU Performance
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Demystifying Complex Workload-DRAM Interactions
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Memory system characterization of deep learning workloads
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Demystifying Complex Workload-DRAM Interactions
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Aging-Aware Request Scheduling for Non-Volatile Main Memory
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DX100: Programmable Data Access Accelerator for Indirection
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OpenDRAM: A Modular, High-performance Soft Memory Controller for DDR4 DRAM
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Scheduling Linux Threads under I/O Chiplet Wall Using cSwitch
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Technology trends in computing hardware and their impacts on high-performance scientific computing Part II: Memory systems, interconnects, and system integration
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Building Data Centers With Optically Connected Memory
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Intelligent Architectures for Intelligent Computing Systems
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Reducing main memory access latency through SDRAM address mapping techniques and access reordering mechanisms
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DAMOV: A New Methodology and Benchmark Suite for Evaluating Data Movement Bottlenecks
inferred← citeshttps://doi.org/10.48550/arxiv.1902.07609openalex-snapshot
Understanding the Interactions of Workloads and DRAM Types: A Comprehensive Experimental Study
inferred← citeshttps://doi.org/10.5555/1298455.1298483openalex-snapshot
Connection handoff policies for TCP offload network interfaces
inferred← citeshttps://doi.org/10.5555/2663510.2663516openalex-snapshot
PseudoNUMA for reducing memory interference in multi-core systems
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Improving bank-level parallelism for irregular applications
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A Multi-core processor for hard real-time systems
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Castell: a heterogeneous cmp architecture scalable to hundreds of processors
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Hardware-Accelerated Range Partitioning
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