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The Spy in the Sandbox
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Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/11605805_1openalex-snapshot
Cache Attacks and Countermeasures: The Case of AES
inferredcites →https://doi.org/10.1007/3-540-68697-5_9openalex-snapshot
Timing Attacks on Implementations of Diffie-Hellman, RSA, DSS, and Other Systems
inferredcites →https://doi.org/10.1007/978-0-387-38162-6openalex-snapshot
Power Analysis Attacks: Revealing the Secrets of Smart Cards
inferredcites →https://doi.org/10.1007/978-3-319-11379-1_15openalex-snapshot
Wait a Minute! A fast, Cross-VM Attack on AES
inferredcites →https://doi.org/10.1007/978-3-319-20550-2_3openalex-snapshot
C5: Cross-Cores Cache Covert Channel
inferredcites →https://doi.org/10.1007/978-3-540-85174-5_12openalex-snapshot
On the Power of Power Analysis in the Real World: A Complete Break of the KeeLoq Code Hopping Scheme
inferredcites →https://doi.org/10.1007/978-3-642-04444-1_13openalex-snapshot
ReFormat: Automatic Reverse Engineering of Encrypted Messages
inferredcites →https://doi.org/10.1007/978-3-642-15031-9_29openalex-snapshot
Algebraic Side-Channel Analysis in the Presence of Errors
inferredcites →https://doi.org/10.1007/978-3-642-23951-9_14openalex-snapshot
Breaking Mifare DESFire MF3ICD40: Power Analysis and Templates in the Real World
inferredcites →https://doi.org/10.1016/j.comnet.2005.01.010openalex-snapshot
Remote timing attacks are practical
inferredcites →https://doi.org/10.1109/risp.1992.213271openalex-snapshot
Lattice scheduling and covert channels
inferredcites →https://doi.org/10.1109/sp.2012.19openalex-snapshot
Memento: Learning Secrets from Process Footprints
inferredcites →https://doi.org/10.1109/sp.2013.23openalex-snapshot
Practical Timing Side Channel Attacks against Kernel Space ASLR
inferredcites →https://doi.org/10.1109/sp.2015.43openalex-snapshot
Last-Level Cache Side-Channel Attacks are Practical
inferredcites →https://doi.org/10.1145/1250662.1250709openalex-snapshot
Adaptive insertion policies for high performance caching
inferredcites →https://doi.org/10.1145/1314466.1314469openalex-snapshot
Yet another MicroArchitectural Attack:
inferredcites →https://doi.org/10.1145/1653662.1653687openalex-snapshot
Hey, you, get off of my cloud
inferredcites →https://doi.org/10.1145/2382196.2382230openalex-snapshot
Cross-VM side channels and their use to extract private keys
inferredcites →https://doi.org/10.1145/2660267.2660356openalex-snapshot
Cross-Tenant Side-Channel Attacks in PaaS Clouds
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.5281/zenodo.59889openalex-extracted
Armageddon: Cache Attacks On Mobile Devices
inferred← citeshttps://doi.org/10.1007/978-3-030-22263-5_80openalex-snapshot
A Survey on Attack Cases Exploiting Computer Architectural Vulnerabilities
inferred← citeshttps://doi.org/10.1007/978-3-030-29962-0_27openalex-snapshot
Mime Artist: Bypassing Whitelisting for the Web with JavaScript Mimicry Attacks
inferred← citeshttps://doi.org/10.1007/978-3-030-58201-2_1openalex-snapshot
Leaky Controller: Cross-VM Memory Controller Covert Channel on Multi-core Systems
inferred← citeshttps://doi.org/10.1007/978-3-030-88040-8_11openalex-snapshot
An Investigation of Microarchitectural Cache-Based Side-Channel Attacks from a Digital Forensic Perspective: Methods of Exploits and Countermeasures
inferred← citeshttps://doi.org/10.1007/978-3-031-15255-9_3openalex-snapshot
Methods of Extracting Parameters of the Processor Caches
inferred← citeshttps://doi.org/10.1007/978-3-031-17143-7_11openalex-snapshot
CPU Port Contention Without SMT
inferred← citeshttps://doi.org/10.1007/978-3-031-17146-8_9openalex-snapshot
Robust and Scalable Process Isolation Against Spectre in the Cloud
inferred← citeshttps://doi.org/10.1007/978-3-031-20974-1_9openalex-snapshot
HyperDetector: Detecting, Isolating, and Mitigating Timing Attacks in Virtualized Environments
inferred← citeshttps://doi.org/10.1007/978-3-031-33488-7_2openalex-snapshot
Layered Binary Templating
inferred← citeshttps://doi.org/10.1007/978-3-031-45395-3_8openalex-snapshot
Microarchitectural Vulnerabilities Introduced, Exploited, and Accelerated by Heterogeneous FPGA-CPU Platforms
inferred← citeshttps://doi.org/10.1007/978-3-031-51479-1_2openalex-snapshot
Indirect Meltdown: Building Novel Side-Channel Attacks from Transient-Execution Attacks
inferred← citeshttps://doi.org/10.1007/978-3-031-78676-1_21openalex-snapshot
Remote Scheduler Contention Attacks
inferred← citeshttps://doi.org/10.1007/978-3-032-06665-7_21openalex-snapshot
Cache and Speculative Side Channel Attacks: A Comprehensive Review
inferred← citeshttps://doi.org/10.1007/978-3-032-07894-0_15openalex-snapshot
Cache Demote for Fast Eviction Set Construction and Page Table Attribute Leakage
inferred← citeshttps://doi.org/10.1007/978-3-032-07894-0_4openalex-snapshot
NICraft: Malicious NIC Firmware-Based Cache Side-Channel Attack
inferred← citeshttps://doi.org/10.1007/978-3-032-08124-7_10openalex-snapshot
GIR-Cache: Mitigating Conflict-Based Cache Side-Channel Attacks via Global Indirect Replacement
inferred← citeshttps://doi.org/10.1007/978-3-319-24174-6_6openalex-snapshot
Practical Memory Deduplication Attacks in Sandboxed Javascript
inferred← citeshttps://doi.org/10.1007/978-3-319-26362-5_3openalex-snapshot
Reverse Engineering Intel Last-Level Cache Complex Addressing Using Performance Counters
inferred← citeshttps://doi.org/10.1007/978-3-319-40667-1_14openalex-snapshot
Flush+Flush: A Fast and Stealthy Cache Attack
inferred← citeshttps://doi.org/10.1007/978-3-319-40667-1_15openalex-snapshot
Rowhammer.js: A Remote Software-Induced Fault Attack in JavaScript
inferred← citeshttps://doi.org/10.1007/978-3-319-42836-9_44openalex-snapshot
Toward Exposing Timing-Based Probing Attacks in Web Applications
inferred← citeshttps://doi.org/10.1007/978-3-319-60876-1_1openalex-snapshot
Malware Guard Extension: Using SGX to Conceal Cache Attacks
inferred← citeshttps://doi.org/10.1007/978-3-319-66399-9_11openalex-snapshot
Practical Keystroke Timing Attacks in Sandboxed JavaScript
inferred← citeshttps://doi.org/10.1007/978-3-319-66399-9_5openalex-snapshot
PerfWeb: How to Violate Web Privacy with Hardware Performance Events
inferred← citeshttps://doi.org/10.1007/978-3-319-66787-4_4openalex-snapshot
CacheZoom: How SGX Amplifies the Power of Cache Attacks
inferred← citeshttps://doi.org/10.1007/978-3-319-70972-7_13openalex-snapshot
Fantastic Timers and Where to Find Them: High-Resolution Microarchitectural Attacks in JavaScript
inferred← citeshttps://doi.org/10.1007/978-3-319-72598-7_13openalex-snapshot
Human-on-the-Loop Automation for Detecting Software Side-Channel Vulnerabilities
inferred← citeshttps://doi.org/10.1007/978-3-319-93387-0_5openalex-snapshot
Drive-By Key-Extraction Cache Attacks from Portable Code
inferred← citeshttps://doi.org/10.1007/978-3-319-97643-3_8openalex-snapshot
Cross-VM Attacks: Attack Taxonomy, Defense Mechanisms, and New Directions
inferred← citeshttps://doi.org/10.1007/978-3-662-53140-2_18openalex-snapshot
Cache Attacks Enable Bulk Key Recovery on the Cloud
inferred← citeshttps://doi.org/10.1007/978-3-662-64322-8_15openalex-snapshot
Speculative Dereferencing: Reviving Foreshadow
inferred← citeshttps://doi.org/10.1007/978-981-95-4674-9_21openalex-snapshot
Detecting and Mitigating Conflict-Based Cache Side-Channel Attacks by Monitoring Ping-Pong Accesses Patterns
inferred← citeshttps://doi.org/10.1007/s11390-019-1979-8openalex-snapshot
An Efficient Approach for Mitigating Covert Storage Channel Attacks in Virtual Machines by the Anti-Detection Criterion
inferred← citeshttps://doi.org/10.1007/s11390-021-1189-zopenalex-snapshot
Improving Performance of Virtual Machine Covert Timing Channel Through Optimized Run-Length Encoding
inferred← citeshttps://doi.org/10.1007/s13389-016-0141-6openalex-snapshot
A survey of microarchitectural timing attacks and countermeasures on contemporary hardware
inferred← citeshttps://doi.org/10.1007/s13389-020-00246-3openalex-snapshot
Adaptive caches as a defense mechanism against cache side-channel attacks
inferred← citeshttps://doi.org/10.1007/s13389-023-00344-yopenalex-snapshot
Breaking KASLR on mobile devices without any use of cache memory (extended version)
inferred← citeshttps://doi.org/10.1007/s41635-017-0025-yopenalex-snapshot
A Survey of Side-Channel Attacks on Caches and Countermeasures
inferred← citeshttps://doi.org/10.1007/s41635-018-0062-1openalex-snapshot
Spy Cartel: Parallelizing Evict+Time-Based Cache Attacks on Last-Level Caches
inferred← citeshttps://doi.org/10.1007/s41635-021-00115-3openalex-snapshot
A Survey on Cache Timing Channel Attacks for Multicore Processors
inferred← citeshttps://doi.org/10.1016/j.comnet.2021.108407openalex-snapshot
Enhanced cache attack on AES applicable on ARM-based devices with new operating systems
inferred← citeshttps://doi.org/10.1016/j.comnet.2021.108550openalex-snapshot
Cache-based characterization: A low-infrastructure, distributed alternative to network-based traffic and application characterization
inferred← citeshttps://doi.org/10.1016/j.cose.2018.09.003openalex-snapshot
When Human cognitive modeling meets PINs: User-independent inter-keystroke timing attacks
inferred← citeshttps://doi.org/10.1016/j.cose.2021.102454openalex-snapshot
Detector + : An approach for detecting, isolating, and preventing timing attacks
inferred← citeshttps://doi.org/10.1016/j.micpro.2016.12.010openalex-snapshot
Timing attack on NoC-based systems: Prime+Probe attack and NoC-based protection
inferred← citeshttps://doi.org/10.1016/j.micpro.2021.104420openalex-snapshot
Secure hybrid replacement policy: Mitigating conflict-based cache side channel attacks
inferred← citeshttps://doi.org/10.1016/j.microrel.2021.114085openalex-snapshot
Verifying cache architecture vulnerabilities using a formal security verification flow
inferred← citeshttps://doi.org/10.1016/j.sysarc.2023.102877openalex-snapshot
Exploiting the microarchitectural leakage of prefetching activities for side-channel attacks
inferred← citeshttps://doi.org/10.1109/access.2020.2980522openalex-snapshot
Meet the Sherlock Holmes’ of Side Channel Leakage: A Survey of Cache SCA Detection Techniques
inferred← citeshttps://doi.org/10.1109/access.2021.3065243openalex-snapshot
Web Browser Privacy: What Do Browsers Say When They Phone Home?
inferred← citeshttps://doi.org/10.1109/access.2021.3101638openalex-snapshot
Runtime Randomized Relocation of Crypto Libraries for Mitigating Cache Attacks
inferred← citeshttps://doi.org/10.1109/apsec48747.2019.00062openalex-snapshot
More Secure Collaborative APIs Resistant to Flush+Reload and Flush+Flush Attacks on ARMv8-A
inferred← citeshttps://doi.org/10.1109/asp-dac66049.2026.11420280openalex-snapshot
PIR-Cache: Mitigating Conflict-Based Cache Side-Channel Attacks via Partial Indirect Replacement
inferred← citeshttps://doi.org/10.1109/comst.2017.2779824openalex-snapshot
Systematic Classification of Side-Channel Attacks: A Case Study for Mobile Devices
inferred← citeshttps://doi.org/10.1109/csf.2019.00010openalex-snapshot
Timing Leaks and Coarse-Grained Clocks
inferred← citeshttps://doi.org/10.1109/csf49147.2020.00032openalex-snapshot
Clockwork: Tracking Remote Timing Attacks
inferred← citeshttps://doi.org/10.1109/dcis51330.2020.9268660openalex-snapshot
Microarchitectural Isolation Guarantees Through Execution Based Signatures
inferred← citeshttps://doi.org/10.1109/dsn48987.2021.00029openalex-snapshot
The Master and Parasite Attack
inferred← citeshttps://doi.org/10.1109/eurosp48549.2020.00027openalex-snapshot
TagBleed: Breaking KASLR on the Isolated Kernel Address Space using Tagged TLBs
inferred← citeshttps://doi.org/10.1109/eurosp51992.2021.00039openalex-snapshot
SoK: In Search of Lost Time: A Review of JavaScript Timers in Browsers
inferred← citeshttps://doi.org/10.1109/eurosp51992.2021.00041openalex-snapshot
Nonce@Once: A Single-Trace EM Side Channel Attack on Several Constant-Time Elliptic Curve Implementations in Mobile Platforms
inferred← citeshttps://doi.org/10.1109/eurosp51992.2021.00048openalex-snapshot
Bypassing memory safety mechanisms through speculative control flow hijacks
inferred← citeshttps://doi.org/10.1109/eurosp51992.2021.00051openalex-snapshot
Aim, Wait, Shoot: How the CacheSniper Technique Improves Unprivileged Cache Attacks
inferred← citeshttps://doi.org/10.1109/eurosp53844.2022.00025openalex-snapshot
LockedDown: Exploiting Contention on Host-GPU PCIe Bus for Fun and Profit
inferred← citeshttps://doi.org/10.1109/eurosp53844.2022.00038openalex-snapshot
xTag: Mitigating Use-After-Free Vulnerabilities via Software-Based Pointer Tagging on Intel x86-64
inferred← citeshttps://doi.org/10.1109/eurosp57164.2023.00044openalex-snapshot
SoK: Analysis of Root Causes and Defense Strategies for Attacks on Microarchitectural Optimizations
inferred← citeshttps://doi.org/10.1109/gcitc60406.2023.10426323openalex-snapshot
Enhancing Prime+Probe Attack Detection Using AI and Machine Learning Techniques for Improved Security
inferred← citeshttps://doi.org/10.1109/host55342.2024.10545405openalex-snapshot
Too Hot to Handle: Novel Thermal Side-Channel in Power Attack-Protected Intel Processors
inferred← citeshttps://doi.org/10.1109/hpca47549.2020.00020openalex-snapshot
A New Side-Channel Vulnerability on Modern Computers by Exploiting Electromagnetic Emanations from the Power Management Unit
inferred← citeshttps://doi.org/10.1109/hpca53966.2022.00013openalex-snapshot
Leaky Frontends: Security Vulnerabilities in Processor Frontends
inferred← citeshttps://doi.org/10.1109/hpca53966.2022.00016openalex-snapshot
unXpec: Breaking Undo-based Safe Speculation
inferred← citeshttps://doi.org/10.1109/hpca56546.2023.10071041openalex-snapshot
Are Randomized Caches Truly Random? Formal Analysis of Randomized-Partitioned Caches
inferred← citeshttps://doi.org/10.1109/iccd.2018.00020openalex-snapshot
A Timing Side-Channel Attack on a Mobile GPU
inferred← citeshttps://doi.org/10.1109/iccd46524.2019.00085openalex-snapshot
AdapTimer: Hardware/Software Collaborative Timer Resistant to Flush-Based Cache Attacks on ARM-FPGA Embedded SoC
inferred← citeshttps://doi.org/10.1109/icoin50884.2021.9333985openalex-snapshot
Constructing Covert Channel on Intel CPU-iGPU platform
inferred← citeshttps://doi.org/10.1109/iiswc66894.2025.00024openalex-snapshot
CASM: A Generalizable and Accessible Security Metric to Evaluate Security of Cache Architectures
inferred← citeshttps://doi.org/10.1109/isca.2018.00058openalex-snapshot
Mobilizing the Micro-Ops: Exploiting Context Sensitive Decoding for Security and Energy Efficiency
inferred← citeshttps://doi.org/10.1109/isca45697.2020.00065openalex-snapshot
Packet Chasing: Spying on Network Packets over a Cache Side-Channel
inferred← citeshttps://doi.org/10.1109/isca52012.2021.00015openalex-snapshot
Zero Inclusion Victim: Isolating Core Caches from Inclusive Last-level Cache Evictions
inferred← citeshttps://doi.org/10.1109/isca52012.2021.00036openalex-snapshot
I See Dead µops: Leaking Secrets via Intel/AMD Micro-Op Caches
inferred← citeshttps://doi.org/10.1109/isca52012.2021.00080openalex-snapshot
Leaky Buddies: Cross-Component Covert Channels on Integrated CPU-GPU Systems
inferred← citeshttps://doi.org/10.1109/iscisc51277.2020.9261920openalex-snapshot
Lurking Eyes: A Method to Detect Side-Channel Attacks on JavaScript and WebAssembly
inferred← citeshttps://doi.org/10.1109/jetcas.2024.3491497openalex-snapshot
Systematical Evasion from Learning-based Microarchitectural Attack Detection Tools
inferred← citeshttps://doi.org/10.1109/lca.2020.2964212openalex-snapshot
Brutus: Refuting the Security Claims of the Cache Timing Randomization Countermeasure Proposed in CEASER
inferred← citeshttps://doi.org/10.1109/metroind4.0iot66048.2025.11121942openalex-snapshot
Challenges in Adapting Flush+Reload to the Web
inferred← citeshttps://doi.org/10.1109/micro.2016.7783740openalex-snapshot
Quantifying and improving the efficiency of hardware-based mobile malware detectors
inferred← citeshttps://doi.org/10.1109/micro.2018.00081openalex-snapshot
CheckMate: Automated Synthesis of Hardware Exploits and Security Litmus Tests
inferred← citeshttps://doi.org/10.1109/micro50266.2020.00016openalex-snapshot
PThammer: Cross-User-Kernel-Boundary Rowhammer through Implicit Accesses
inferred← citeshttps://doi.org/10.1109/micro61859.2024.00088openalex-snapshot
Veiled Pathways: Investigating Covert and Side Channels Within GPU Uncore
inferred← citeshttps://doi.org/10.1109/mm.2023.3273457openalex-snapshot
There’s Always a Bigger Fish: A Clarifying Analysis of a Machine-Learning-Assisted Side-Channel Attack
inferred← citeshttps://doi.org/10.1109/sbcci.2016.7724051openalex-snapshot
Side channel attack on NoC-based MPSoCs are practical: NoC Prime+Probe attack
inferred← citeshttps://doi.org/10.1109/seed61283.2024.00012openalex-snapshot
Tail Victims in Termination Timing Channel Defenses Beyond Cryptographic Kernels
inferred← citeshttps://doi.org/10.1109/sp.2016.63openalex-snapshot
Dedup Est Machina: Memory Deduplication as an Advanced Exploitation Vector
inferred← citeshttps://doi.org/10.1109/sp.2018.00022openalex-snapshot
Grand Pwning Unit: Accelerating Microarchitectural Attacks with the GPU
inferred← citeshttps://doi.org/10.1109/sp.2019.00002openalex-snapshot
Spectre Attacks: Exploiting Speculative Execution
inferred← citeshttps://doi.org/10.1109/sp.2019.00004openalex-snapshot
Attack Directories, Not Caches: Side Channel Attacks in a Non-Inclusive World
inferred← citeshttps://doi.org/10.1109/sp.2019.00042openalex-snapshot
Theory and Practice of Finding Eviction Sets
inferred← citeshttps://doi.org/10.1109/sp.2019.00062openalex-snapshot
The 9 Lives of Bleichenbacher's CAT: New Cache ATtacks on TLS Implementations
inferred← citeshttps://doi.org/10.1109/sp40000.2020.00031openalex-snapshot
Dragonblood: Analyzing the Dragonfly Handshake of WPA3 and EAP-pwd
inferred← citeshttps://doi.org/10.1109/sp40000.2020.00082openalex-snapshot
NetCAT: Practical Cache Attacks from the Network
inferred← citeshttps://doi.org/10.1109/sp40001.2021.00011openalex-snapshot
Systematic Analysis of Randomization-based Protected Cache Architectures
inferred← citeshttps://doi.org/10.1109/sp40001.2021.00050openalex-snapshot
Randomized Last-Level Caches Are Still Vulnerable to Cache Side-Channel Attacks! But We Can Fix It
inferred← citeshttps://doi.org/10.1109/sp40001.2021.00059openalex-snapshot
Invisible Probe: Timing Attacks with PCIe Congestion Side-channel
inferred← citeshttps://doi.org/10.1109/sp46214.2022.9833692openalex-snapshot
Adversarial Prefetch: New Cross-Core Cache Side Channel Attacks
inferred← citeshttps://doi.org/10.1109/sp46214.2022.9833711openalex-snapshot
Spook.js: Attacking Chrome Strict Site Isolation via Speculative Execution
inferred← citeshttps://doi.org/10.1109/sp46214.2022.9833773openalex-snapshot
Graphics Peeping Unit: Exploiting EM Side-Channel Information of GPUs to Eavesdrop on Your Neighbors
inferred← citeshttps://doi.org/10.1109/sp46215.2023.10179283openalex-snapshot
DevIOus: Device-Driven Side-Channel Attacks on the IOMMU
inferred← citeshttps://doi.org/10.1109/sp46215.2023.10179440openalex-snapshot
Scatter and Split Securely: Defeating Cache Contention and Occupancy Attacks
inferred← citeshttps://doi.org/10.1109/sp61157.2025.00008openalex-snapshot
Ceviche: Capability-Enhanced Secure Virtualization of Caches
inferred← citeshttps://doi.org/10.1109/sp61157.2025.00075openalex-snapshot
SoK: Software Compartmentalization
inferred← citeshttps://doi.org/10.1109/sp61157.2025.00098openalex-snapshot
SLAP: Data Speculation Attacks via Load Address Prediction on Apple Silicon
inferred← citeshttps://doi.org/10.1109/sp61157.2025.00264openalex-snapshot
Slice+Slice Baby: Generating Last-Level Cache Eviction Sets in the Blink of an Eye
inferred← citeshttps://doi.org/10.1109/sp63933.2026.00066openalex-snapshot
Transient Architectural Execution: From Weird Gates to Weird Programs
inferred← citeshttps://doi.org/10.1109/sp63933.2026.00106openalex-snapshot
Keytar: Practical Keystroke Timing Attacks and Input Reconstruction
inferred← citeshttps://doi.org/10.1109/sp63933.2026.00192openalex-snapshot
RISCy Cache Coherence: Timer-Free Architectural Cache Attacks via Instruction/Data Cache Incoherence
inferred← citeshttps://doi.org/10.1109/sp63933.2026.00254openalex-snapshot
Practical Covert Channel Across Isolated Browser Instances via GPU Command Queue Contention
inferred← citeshttps://doi.org/10.1109/tcad.2024.3392082openalex-snapshot
SnapMem: Hardware/Software Cooperative Memory Resistant to Cache-Related Attacks on ARM-FPGA Embedded SoC
inferred← citeshttps://doi.org/10.1109/tdsc.2019.2944624openalex-snapshot
Side Channel Attacks on GPUs
inferred← citeshttps://doi.org/10.1109/tdsc.2020.2988369openalex-snapshot
Website Fingerprinting Through the Cache Occupancy Channel and its Real World Practicality
inferred← citeshttps://doi.org/10.1109/tdsc.2021.3117145openalex-snapshot
XAI-Based Microarchitectural Side-Channel Analysis for Website Fingerprinting Attacks and Defenses
inferred← citeshttps://doi.org/10.1109/tdsc.2022.3214666openalex-snapshot
Implicit Hammer : Cross-Privilege-Boundary Rowhammer Through Implicit Accesses
inferred← citeshttps://doi.org/10.1109/tdsc.2025.3617019openalex-snapshot
Fish and Chips: On the Root Causes of Co-Located Website-Fingerprinting Attacks
inferred← citeshttps://doi.org/10.1109/tifs.2020.3004264openalex-snapshot
Detecting Hardware-Assisted Virtualization With Inconspicuous Features
inferred← citeshttps://doi.org/10.1109/tifs.2023.3272748openalex-snapshot
MAD-EN: Microarchitectural Attack Detection Through System-Wide Energy Consumption
inferred← citeshttps://doi.org/10.1109/tifs.2024.3368862openalex-snapshot
RECAST: Mitigating Conflict-Based Cache Attacks Through Fine-Grained Dynamic Mapping
inferred← citeshttps://doi.org/10.1109/tmscs.2016.2550438openalex-snapshot
Cross-VM Cache Attacks on AES
inferred← citeshttps://doi.org/10.1109/tnet.2023.3294019openalex-snapshot
Interface-Based Side Channel in TEE-Assisted Networked Services
inferred← citeshttps://doi.org/10.1109/trustcom63139.2024.00082openalex-snapshot
You Are as You Type: Investigating the Influence of Timestamp Accuracy on the Robustness of Keystroke Biometrics
inferred← citeshttps://doi.org/10.1145/2897845.2897867openalex-snapshot
Cross Processor Cache Attacks
inferred← citeshttps://doi.org/10.1145/2939918.2939922openalex-snapshot
Exploiting Data-Usage Statistics for Website Fingerprinting Attacks on Android
inferred← citeshttps://doi.org/10.1145/2976749.2978356openalex-snapshot
Prefetch Side-Channel Attacks
inferred← citeshttps://doi.org/10.1145/2976749.2978360openalex-snapshot
Return-Oriented Flush-Reload Side Channels on ARM and Their Implications for Android Devices
inferred← citeshttps://doi.org/10.1145/2991079.2991113openalex-snapshot
Efficient, adversarial neighbor discovery using logical channels on Microsoft Azure
inferred← citeshttps://doi.org/10.1145/3052973.3053007openalex-snapshot
Detecting Privileged Side-Channel Attacks in Shielded Execution with Déjà Vu
inferred← citeshttps://doi.org/10.1145/3052973.3053036openalex-snapshot
Cache-Based Application Detection in the Cloud Using Machine Learning
inferred← citeshttps://doi.org/10.1145/3079856.3080222openalex-snapshot
Secure Hierarchy-Aware Cache Replacement Policy (SHARP)
inferred← citeshttps://doi.org/10.1145/3132747.3132781openalex-snapshot
Secure Page Fusion with VUsion
inferred← citeshttps://doi.org/10.1145/3133956.3133966openalex-snapshot
Most Websites Don't Need to Vibrate
inferred← citeshttps://doi.org/10.1145/3133956.3134038openalex-snapshot
Leaky Cauldron on the Dark Land
inferred← citeshttps://doi.org/10.1145/3140659.3080222openalex-snapshot
Secure Hierarchy-Aware Cache Replacement Policy (SHARP)
inferred← citeshttps://doi.org/10.1145/3199478.3199488openalex-snapshot
Cache Attack on AES for Android Smartphone
inferred← citeshttps://doi.org/10.1145/3212480.3212489openalex-snapshot
Tracking Private Browsing Sessions using CPU-based Covert Channels
inferred← citeshttps://doi.org/10.1145/3243734.3243861openalex-snapshot
An Exploratory Analysis of Microcode as a Building Block for System Defenses
inferred← citeshttps://doi.org/10.1145/3274694.3274715openalex-snapshot
Analyzing Cache Side Channels Using Deep Neural Networks
inferred← citeshttps://doi.org/10.1145/3290390openalex-snapshot
CT-wasm: type-driven secure cryptography for the web ecosystem
inferred← citeshttps://doi.org/10.1145/3297280.3297470openalex-snapshot
Spectre without shared memory
inferred← citeshttps://doi.org/10.1145/3320269.3384746openalex-snapshot
Take A Way: Exploring the Security Implications of AMD's Cache Way Predictors
inferred← citeshttps://doi.org/10.1145/3321705.3329804openalex-snapshot
Undermining User Privacy on Mobile Devices Using AI
inferred← citeshttps://doi.org/10.1145/3338508.3359574openalex-snapshot
Adaptive Caches as a Defense Mechanism Against Cache Side-Channel Attacks
inferred← citeshttps://doi.org/10.1145/3357613.3357627openalex-snapshot
Actual and historical state of side channel attacks theory
inferred← citeshttps://doi.org/10.1145/3394885.3431638openalex-snapshot
Micro-architectural Cache Side-Channel Attacks and Countermeasures
inferred← citeshttps://doi.org/10.1145/3409959openalex-snapshot
Game Theory based Cyber-Insurance to Cover Potential Loss from Mobile Malware Exploitation
inferred← citeshttps://doi.org/10.1145/3427228.3427295openalex-snapshot
Dragonblood is Still Leaking: Practical Cache-based Side-Channel in the Wild
inferred← citeshttps://doi.org/10.1145/3428215openalex-snapshot
Exposing cache timing side-channel leaks through out-of-order symbolic execution
inferred← citeshttps://doi.org/10.1145/3433210.3437517openalex-snapshot
Red Alert for Power Leakage: Exploiting Intel RAPL-Induced Side Channels
inferred← citeshttps://doi.org/10.1145/3460120.3484815openalex-snapshot
Let's Downgrade Let's Encrypt
inferred← citeshttps://doi.org/10.1145/3466752.3480079openalex-snapshot
UC-Check: Characterizing Micro-operation Caches in x86 Processors and Implications in Security and Performance
inferred← citeshttps://doi.org/10.1145/3471936openalex-snapshot
A Comprehensive Survey of Attacks without Physical Access Targeting Hardware Vulnerabilities in IoT/IIoT Devices, and Their Detection Mechanisms
inferred← citeshttps://doi.org/10.1145/3485832.3485902openalex-snapshot
An Exploration of ARM System-Level Cache and GPU Side Channels
inferred← citeshttps://doi.org/10.1145/3488932.3517411openalex-snapshot
Port Contention Goes Portable
inferred← citeshttps://doi.org/10.1145/3544102openalex-snapshot
Microarchitectural Attacks in Heterogeneous Systems: A Survey
inferred← citeshttps://doi.org/10.1145/3560834.3563823openalex-snapshot
Breaking KASLR on Mobile Devices without Any Use of Cache Memory
inferred← citeshttps://doi.org/10.1145/3564625.3567979openalex-snapshot
DF-SCA: Dynamic Frequency Side Channel Attacks are Practical
inferred← citeshttps://doi.org/10.1145/3568160.3570227openalex-snapshot
More Secure Collaborative APIs resistant to Flush-Based Cache Attacks on Cortex-A9 Based Automotive System
inferred← citeshttps://doi.org/10.1145/3575693.3575700openalex-snapshot
Hacky Racers: Exploiting Instruction-Level Parallelism to Generate Stealthy Fine-Grained Timers
inferred← citeshttps://doi.org/10.1145/3576915.3616611openalex-snapshot
iLeakage: Browser-based Timerless Speculative Execution Attacks on Apple Devices
inferred← citeshttps://doi.org/10.1145/3576915.3616655openalex-snapshot
The Danger of Minimum Exposures: Understanding Cross-App Information Leaks on iOS through Multi-Side-Channel Learning
inferred← citeshttps://doi.org/10.1145/3579856.3582838openalex-snapshot
IOTLB-SC: An Accelerator-Independent Leakage Source in Modern Cloud Systems
inferred← citeshttps://doi.org/10.1145/3579856.3595794openalex-snapshot
CacheFX: A Framework for Evaluating Cache Security
inferred← citeshttps://doi.org/10.1145/3579856.3595803openalex-snapshot
FlushTime: Towards Mitigating Flush-based Cache Attacks via Collaborating Flush Instructions and Timers on ARMv8-A
inferred← citeshttps://doi.org/10.1145/3607199.3607202openalex-snapshot
CTPP: A Fast and Stealth Algorithm for Searching Eviction Sets on Intel Processors
inferred← citeshttps://doi.org/10.1145/3613424.3614275openalex-snapshot
Phantom: Exploiting Decoder-detectable Mispredictions
inferred← citeshttps://doi.org/10.1145/3620665.3640403openalex-snapshot
Last-Level Cache Side-Channel Attacks Are Feasible in the Modern Public Cloud
inferred← citeshttps://doi.org/10.1145/3627106.3627187openalex-snapshot
No Forking Way: Detecting Cloning Attacks on Intel SGX Applications
inferred← citeshttps://doi.org/10.1145/3627106.3627191openalex-snapshot
DefWeb: Defending User Privacy against Cache-based Website Fingerprinting Attacks with Intelligent Noise Injection
inferred← citeshttps://doi.org/10.1145/3708821.3710819openalex-snapshot
AVXProbe: Enhancing Website Fingerprinting with Side-Channel-Assisted Kernel-Level Traces
inferred← citeshttps://doi.org/10.1145/3708821.3710844openalex-snapshot
EXAM: Exploiting Exclusive System-Level Cache in Apple M-Series SoCs for Enhanced Cache Occupancy Attacks
inferred← citeshttps://doi.org/10.1145/3725843.3756029openalex-snapshot
Understanding and Mitigating Covert Channel and Side Channel Vulnerabilities Introduced by RowHammer Defenses
inferred← citeshttps://doi.org/10.1145/3842387openalex-snapshot
User Privacy Attacks through Self-Modifying Code Conflicts
inferred← citeshttps://doi.org/10.1186/s13677-017-0101-4openalex-snapshot
Keep the PokerFace on! Thwarting cache side channel attacks by memory bus monitoring and cache obfuscation
inferred← citeshttps://doi.org/10.1186/s42400-019-0042-yopenalex-snapshot
Malware Guard Extension: abusing Intel SGX to conceal cache attacks
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