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Identifying Power-Efficient Multicore Cache Hierarchies via Reuse Distance Analysis
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/978-3-642-11970-5_15openalex-snapshot
Is Reuse Distance Applicable to Data Locality Analysis on Chip Multiprocessors?
inferredcites →https://doi.org/10.1007/s11390-010-9321-5openalex-snapshot
Hierarchical Cache Directory for CMP
inferredcites →https://doi.org/10.1109/hpca.2006.1598109openalex-snapshot
CMP Design Space Exploration Subject to Physical Constraints
inferredcites →https://doi.org/10.1109/hpca.2010.5416635openalex-snapshot
Graphite: A distributed parallel simulator for multicores
inferredcites →https://doi.org/10.1109/iiswc.2006.302743openalex-snapshot
MineBench: A Benchmark Suite for Data Mining Workloads
inferredcites →https://doi.org/10.1109/iiswc.2011.6114194openalex-snapshot
The Multi-Program Performance Model: Debunking current practice in multi-core simulation
inferredcites →https://doi.org/10.1109/ipdpsw.2010.5470780openalex-snapshot
Multicore-aware reuse distance analysis
inferredcites →https://doi.org/10.1109/isca.2008.15openalex-snapshot
3D-Stacked Memory Architectures for Multi-core Processors
inferredcites →https://doi.org/10.1109/ispass.2004.1291352openalex-snapshot
StatCache: A probabilistic approach to efficient and accurate data locality analysis
inferredcites →https://doi.org/10.1109/ispass.2005.1430567openalex-snapshot
Power-Performance Implications of Thread-level Parallelism on Chip Multiprocessors
inferredcites →https://doi.org/10.1109/ispass.2010.5452069openalex-snapshot
StatStack: Efficient modeling of LRU caches
inferredcites →https://doi.org/10.1109/nocs.2012.31openalex-snapshot
DSENT - A Tool Connecting Emerging Photonics with Electronics for Opto-Electronic Networks-on-Chip Modeling
inferredcites →https://doi.org/10.1109/pact.2003.1238004openalex-snapshot
Miss rate prediction across all program inputs
inferredcites →https://doi.org/10.1109/pact.2005.42openalex-snapshot
Maximizing CMP throughput with mediocre cores
inferredcites →https://doi.org/10.1109/pact.2011.58openalex-snapshot
Coherent Profiles: Enabling Efficient Reuse Distance Analysis of Multicore Scaling for Loop-based Parallel Programs
inferredcites →https://doi.org/10.1145/1064212.1064232openalex-snapshot
Fast data-locality profiling of native execution
inferredcites →https://doi.org/10.1145/1105734.1105739openalex-snapshot
Exploring the cache design space for large scale CMPs
inferredcites →https://doi.org/10.1145/1168857.1168881openalex-snapshot
Accurate and efficient regression modeling for microarchitectural performance and power prediction
inferredcites →https://doi.org/10.1145/1168857.1168882openalex-snapshot
Efficiently exploring architectural design spaces via predictive modeling
inferredcites →https://doi.org/10.1145/1394608.1382159openalex-snapshot
3D-Stacked Memory Architectures for Multi-core Processors
inferredcites →https://doi.org/10.1145/1534909.1534910openalex-snapshot
A mechanistic performance model for superscalar out-of-order processors
inferredcites →https://doi.org/10.1145/1552309.1552310openalex-snapshot
Program locality analysis using reuse distance
inferredcites →https://doi.org/10.1145/1854273.1854286openalex-snapshot
Accelerating multicore reuse distance analysis with sampling and parallelization
inferredcites →https://doi.org/10.1145/1944862.1944885openalex-snapshot
Fast modeling of shared caches in multicore systems
inferredcites →https://doi.org/10.1145/2247684.2247687openalex-snapshot
Identifying optimal multicore cache hierarchies for loop-based parallel programs via reuse distance analysis
inferredcites →https://doi.org/10.1145/2427631.2427632openalex-snapshot
Efficient Reuse Distance Analysis of Multicore Scaling for Loop-Based Parallel Programs
inferredcites →https://doi.org/10.1145/2485922.2485965openalex-snapshot
Studying multicore processor scaling via reuse distance analysis
inferredcites →https://doi.org/10.1145/3559009openalex-snapshot
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques
inferredcites →https://doi.org/10.1145/357980.357997openalex-snapshot
The working set model for program behavior
inferredcites →https://doi.org/10.1145/363095.363141openalex-snapshot
The working set model for program behavior
inferredcites →https://doi.org/10.1145/780822.781159openalex-snapshot
Predicting whole-program locality through reuse distance analysis
inferredcites →https://doi.org/10.1145/781131.781159openalex-snapshot
Predicting whole-program locality through reuse distance analysis
inferredcites →https://doi.org/10.1147/sj.92.0078openalex-snapshot
Evaluation techniques for storage hierarchies
inferredcites →https://doi.org/10.5555/645988.674164openalex-snapshot
Exploring the Design Space of Future CMPs
inferredcites →https://doi.org/10.5555/942806.943841openalex-snapshot
Miss rate prediction across all program inputs
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/s11227-021-03949-4openalex-snapshot
PPT-Multicore: performance prediction of OpenMP applications using reuse profiles and analytical modeling
inferred← citeshttps://doi.org/10.1016/j.simpat.2018.12.003openalex-snapshot
Analyzing data locality in GPU kernels using memory footprint analysis
inferred← citeshttps://doi.org/10.1109/hpca.2019.00056openalex-snapshot
Featherlight Reuse-Distance Measurement
inferred← citeshttps://doi.org/10.1109/iccsd.2019.8842919openalex-snapshot
An Improved Scheme of Victim Replication in Tiled Chip Multiprocessors
inferred← citeshttps://doi.org/10.1109/lca.2017.2695178openalex-snapshot
Guiding Locality Optimizations for Graph Computations via Reuse Distance Analysis
inferred← citeshttps://doi.org/10.1109/pccc.2017.8280444openalex-snapshot
Optimizing locality in graph computations using reuse distance profiles
inferred← citeshttps://doi.org/10.1109/tc.2024.3416747openalex-snapshot
CBANA: A Lightweight, Efficient, and Flexible Cache Behavior Analysis Framework
inferred← citeshttps://doi.org/10.1109/tmag.2023.3267467openalex-snapshot
MRAM-Based Cache System Design and Policy Optimization for RISC-V Multi-Core CPUs
inferred← citeshttps://doi.org/10.1109/tpds.2021.3066308openalex-snapshot
ETICA: Efficient Two-Level I/O Caching Architecture for Virtualized Platforms
inferred← citeshttps://doi.org/10.1145/3291051openalex-snapshot
Efficient Cache Performance Modeling in GPUs Using Reuse Distance Analysis
inferred← citeshttps://doi.org/10.1145/3577193.3593740openalex-snapshot
FLORIA: A Fast and Featherlight Approach for Predicting Cache Performance
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