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Proceedings of the International Conference on Parallel Architectures and Compilation Techniques
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What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1002/cpe.851openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/s11432-024-4071-6openalex-snapshot
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inferred← citeshttps://doi.org/10.1016/j.future.2025.108165openalex-snapshot
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inferred← citeshttps://doi.org/10.1016/j.neucom.2025.130458openalex-snapshot
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inferred← citeshttps://doi.org/10.1016/j.sysarc.2025.103427openalex-snapshot
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inferred← citeshttps://doi.org/10.1145/1062247.1062250openalex-snapshot
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inferred← citeshttps://doi.org/10.1145/1242531.1242564openalex-snapshot
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inferred← citeshttps://doi.org/10.1145/1250727.1250731openalex-snapshot
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inferred← citeshttps://doi.org/10.1145/1353445.1353451openalex-snapshot
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inferred← citeshttps://doi.org/10.1145/1400112.1400115openalex-snapshot
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inferred← citeshttps://doi.org/10.1145/2384616.2384643openalex-snapshot
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inferred← citeshttps://doi.org/10.1145/2442116.2442132openalex-snapshot
High-performance and low-energy buffer mapping method for multiprocessor DSP systems
inferred← citeshttps://doi.org/10.1145/2483852.2483866openalex-snapshot
Nonblocking algorithms and scalable multicore programming
inferred← citeshttps://doi.org/10.1145/2660251openalex-snapshot
Automatic parallelization of a class of irregular loops for distributed memory systems
inferred← citeshttps://doi.org/10.1145/2851503openalex-snapshot
Identifying Power-Efficient Multicore Cache Hierarchies via Reuse Distance Analysis
inferred← citeshttps://doi.org/10.1145/3178487.3178500openalex-snapshot
Register optimizations for stencils on GPUs
inferred← citeshttps://doi.org/10.1145/3323055openalex-snapshot
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inferred← citeshttps://doi.org/10.1145/360128.360140openalex-snapshot
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inferred← citeshttps://doi.org/10.1145/3625549.3658691openalex-snapshot
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inferred← citeshttps://doi.org/10.1145/3626183.3659985openalex-snapshot
Minimum Cost Loop Nests for Contraction of a Sparse Tensor with a Tensor Network
inferred← citeshttps://doi.org/10.1145/3648358openalex-snapshot
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inferred← citeshttps://doi.org/10.1145/3656019.3689613openalex-snapshot
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inferred← citeshttps://doi.org/10.1145/3663672openalex-snapshot
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inferred← citeshttps://doi.org/10.1145/857076.857077openalex-snapshot
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inferred← citeshttps://doi.org/10.1145/980152.980157openalex-snapshot
Temperature-aware microarchitecture
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